Category: Moore’s Law

SiP Metrics – Is there a Moore’s Law equivalent?

 

In the landmark paper of 1965, Gordon Moore[1] made an observation stating that with cost of manufacturing per device falling, it becomes economical to pack more and more devices in an IC chip. In his paper, Moore projected the number of devices in an IC chip would double every one to two years. This observation soon took the form of a proxy for future growth estimates in the semiconductor industry.

For decades, Moore’s law has been the benchmark for semiconductor technology development, eventually becoming a roadmap and a self-fulfilling prophecy for IC development.  Figure 1[2] shows the growth of the number of devices in a semiconductor chip over time and tracks well with Moore’s projection.

SC Tech Trends vs Moore's Law
Figure 1: Product functions per chip vs. time (tracking Moore’s law).

The popularity of Moore’s law was in its simplicity. The number of transistors is a meaningful and simple measure and generally tracks with system development. However, Moore’s law is not universally applicable to all microelectronic devices. One such device is a SiP.

SiPs are emerging as a distinct class of microelectronic products because of their unique ability to integrate silicon of different process technologies such as Digital, Analog, Power, and DRAM as well as include passives and other devices to build integrated solutions. It is therefore useful to study SiP development and see if there are logical Moore’s Law like trends that are evident. In the next section, we will discuss a possible trend for SiPs, the reduction of external connections, and make a proposal for a growth metric for SiP technologies.

The ultimate goal of SiPs is to enable a fully integrated stand-alone autonomous electronic system. Such a SiP would have its own power supply, microprocessor, input, output and passive devices and be capable of performing the required function entirely with no external wired connection. An ideal SiP would have no external pins (if it had its own power source) or only have 2 pins – for power and ground.  Since one of the purposes of a SiP is to reduce the number of wired connections we propose a figure of merit based on the reduction of these connections provided by using a SiP.

SiP “Figure of Merit” (FOM):  One can define a FOM based on the number of externally wired connections in a SiP. If a SiP reduces the number of connections of the chips on board (COB) by half, then FOM is 0.5.  If the SiP completely eliminates the need for external connections, therefore creating an autonomous system, then, in this ideal case, the FOM is 1. A system with no SiP means there was no reduction in interconnections to form a system. Such a system would have a FOM of 0.    Therefore, FOM can be defined by the formula,

 \text{Figure of Merit (FOM)} = \frac{\text{Number of Connections with COB}-\text{Number of Connections with SiP}}{\text{Number of Connections with COB}}

In the chart (Figure 2) below there are a few examples FOM. A real-life test case system “A” is also included for reference. In system “A” by using SiP the total number of interconnects dropped from about 1200 to 700 pins which gives a FOM of 0.42.

SiP Figure of Merit
Figure 2: Figure of Merit (COB: Chip on Board, individually packaged devices mounted on system board).

As discussed in a previous post, one of the key areas holding back the development of SiPs is the lack of a metric to measure their effectiveness and development.  In this blog we have attempted to put forward a proposed metric tied to the reduction in number of external connections due to a SiP integration, which in turn correlates with the level of integration as a system. We will be using this metric to help demonstrate the value of our SiP devices.

We welcome your comments on this topic as we attempt to set a metric that can be used across the industry.

 

[1]  Cramming more components onto integrated circuits, Gordon Moore, Electronics, Volume 38, Number 8, April 19, 1965

[2] International Technology Roadmap for Semiconductors (ITRS) 2007

System in Package: the Complement to Moore’s Law

 

Moore’s Law has served us well for over a half of a century.  It drove the semiconductor (SC) process technology roadmap.  It got us to think about putting more transistors on an integrated circuit to the point where it is no longer a nightmare to consider billions of transistors on one piece of silicon.  In fact, several years ago I began to use the phrase “transistors are becoming a buck a billion” to put a new perspective on the success of Moore’s Law.

But even with the great success the SC industry has had, we continue to find ourselves unable to accomplish the ultimate goal, a complete system on a chip.  Yes, we talk about System on Chip (SoC) technology as the solution (now what was the problem again?).  However, the advancements in IC technology have actually defeated the primary goal of SoC, the integration of a complete system on a single piece of silicon.  In the past I have actually suggested that it should be SSoC rather than SoC as all we have been able to do is a Sub-System on a Chip.

So why can’t we put a complete system on one device?  Why haven’t we, through all of the advances, been able to truly get the entire system on a single piece of silicon?  Let’s take a step back and look at the type of components that go into a system.  They include processors, memories, analog, power management, RF communications, sensors, energy scavengers, and many more. Each of which use a different SC process that has evolved in part by chasing Moore’s Law to optimize its peak performance.  We no longer have just one IC manufacturing process.  We have created processes to be optimized for specific needs.  There is a specific process for high performance microprocessors, another process for memories, another for high performance audio, another for power management, another for RF circuits . . . have you caught the drift?

Process Technology Diverges as it is optimized
This figure shows how optimized process diverge from each other

You can argue that an optimal SC process should be able to include all of the different types of components.  However, the laws of physics as we know them today don’t allow this to happen.  We can mix different types of components onto a single process but significant compromises will have to be made.  The only way to achieve the optimal performance out of a system is to have each component use its own optimized process.  So you end up with a design where all of the digital circuits are integrated into a digital SoC , the analog circuits into an analog SoC, the power circuits into a power SoC, and so forth. (See figure to the right)

That leads me to a complementary capability introduced to the industry about a decade or so ago.  This new ability enabled different components from different SC processes to be integrated into a single package that can be used by system designers.  There are several ways to accomplish this and they have different names, such as Multi-Chip-Module (MCM), System on Module (SoM), or System in Package (SiP).  From our perspective, the concept of a System in Package (SiP) best describes the ultimate concept.  The reason for our use of SiP is simple:

  • A System consists of many components including analog, digital, and power ICs, as well as other active circuits like transistors, diodes, MeMs and sensors. You also need to include passive devices like resistors, capacitors and inductors.
  • In-Package means all of the components that make up the system are in a Single Package that looks like an IC.

So to the outside world a SiP looks like a complete electronic system in single package.

However, as a system designer, even with SiP technology bringing to together different SoC processes along with other electronic components a true complete System-In-Package is still hard to achieve.  I’ll give you a hint why I am saying this – the SiPs today still have pins on the package.  The ultimate electronic system should not need pins, right?  But I’ll save that discussion to a later post.  Let me get back to the topic.

What brought us to needing SiP technology can be best seen by going back to the origin of the integrated circuit and following its evolution.  But just as with the earlier “not needing pins” comment, we will discuss this evolution in more detail in a later blog.  For now I will simply say that as we optimized the manufacturing processes for the different kinds of circuits, the ability to put those different kinds of circuits onto the same SoC became difficult, if not impossible.  The only way to continue to integrate these different SoCs is through the use of a SiP.  The following figure attempts to describe that issue.

SiP Integrates multiple SoC processes
In this figure we can see that as we take advantage of SoC technology, it takes longer to create, costs more to develop and becomes specific to only one aspect of IC technology. But once the SoCs are created it becomes easy to integrate them together either on a PCB or SiP. As the system becomes more complex SiP is the better choice for the integration of heterogeneous systems.

 

Now that we went through why SiPs are needed, if you want more information on how Octavo Systems is bringing this technology to the masses check out our series on SiP technology and the Challenges here.

 

A Complementary Semiconductor Roadmap: System-In-Package (SiP) and the Challenges Ahead

 

Since the early 1960s, advances in semiconductor technology have been tracking Moore’s law. This “law”, based on a paper by Gordon Moore[i], states that the number of transistors per chip will double about every 18 months.  For decades Moore’s law has been the overarching benchmark for development in the Semiconductor industry, especially in regards to System-On-Chip (SoC) development.

Moore’s law, however, is not endlessly sustainable (for reasons we discuss in this post) and an alternative approach was needed. Since the 2000’s there has been a recognition that System-In-Package devices (SiPs) indeed have a distinct role in semiconductor technology development.Moore's Law and SipS The 2009 ITRS (International Technology Roadmap for Semiconductors) on SiPs (Figure to the Right) reflects this recognition and outlines the technologies that are uniquely enabled by SiP technology. It is now becoming evident that SoC progression and Moore’s law cannot solely define the semiconductor roadmap and SiPs play a major and complementary role.

Will SiPs emulate the rapid advancements seen in SoCs? At Octavo we believe the answer is YES. We believe there are key areas for innovation to spur the wider and faster adoption of SiPs.  Outlined below are a few of the challenges that we are working to address.

First, a meaningful metric for SiP progression similar to Moore’s law is required.  A standardized metric will allow comparison and evaluation of SiP technologies to one another and compare solutions. Moore’s law simply uses the number of transistor in a chip as the metric.  For System-in-Package the metric will have to be different and likely more complex. While it may include the number of transistors as with SoCs, extent of heterogeneous functional integration and the hierarchy of system integration achieved by SiP are some of the few factors that could be taken into consideration to define a meaningful metric. (We propose our metric in this post)

Secondly, SiP development will require development of supporting manufacturing infrastructure. SiPs by necessity will use most of the existing SoC manufacturing base which is not yet optimized for SiPs. This will bring many challenges[ii] to SiP development.

Here are a few of these challenges

  1. Supply chain management for constituent SoCs
  2. A uniform definition of known-good-die (KGD) between supplier and user
  3. Complexity of system design which includes passives, MEMs, and other non-traditional circuit elements
  4. Packaging and thermal management
  5. Functional testing
  6. Rapid prototyping and validation
  7. High volume manufacturing
  8. Reliability in unusual or harsh environments

Check back as we will dive into each of these challenges in the upcoming months.  You can also sign up for our newsletter or follow us on Twitter, Facebook, or LinkedIn to get all of the latest news.


[i]  Cramming more components onto integrated circuits, Gordon Moore, Electronics, Volume 38, Number 8, April 19, 1965

[ii] The road ahead for SiPs, Darvin Edwards & Masood Murtuza, Solid State Technology, Feb. 2011.