OSD32MP1 Power System Overview

Published On: September, 9, 2020 By: Neeraj Dantu

The OSD32MP15x, the STM32MP15x System in Package (SiP), contains the STPMIC1A Power Management Integrated Circuit (PMIC) for power management. The PMIC is responsible for powering the STM32MP15x processor, Oscillator, EEPROM, and DDR. It provides configurable power-up and power-down sequencing required by the processor through programmable non-volatile memory (NVM). The PMIC contains six (6) adjustable LDOs, four (4) adjustable Buck convertors and one (1) Boost converter. The OSD32MP15x integrates the PMIC as well as the interface between the STM32MP15x and STPMIC1A for configuration.

This application note describes the hardware configuration of the OSD32MP15x and how the STPMIC1A and STM32MP15x are connected within the OSD32MP15x. It also describes the features and functions of the STPMIC1A inside of the SiP.  It is designed to be an introduction to the power system of the OSD32Mp1 that can be used to optimize power consumption leveraging different low power modes and when creating a power budget.

OSD32MP15x PMIC Hardware

The OSD32MP15x has two required power inputs: VIN, the main power input, and VBAT, the backup battery power input. There are additional optional power inputs for system power outputs. The figure below shows the power inputs and output of the OSD32MP15x.

 

The OSD32MP15x integrates the connections between STM32MP15x and STPMIC1A to minimize the external connections required in the design. The figure below shows the OSD32MP15x pins for the power subsystem. Specifically, it shows pins that require external configuration, pins that can be optionally configured, and pins that have been internally connected and brought out as test points. Note that all the VDD pins of OSD32MP15x need to be tied together for the device to function properly. The Power Configuration Pins table describes the intended function of each of these pins and their role in OSD32MP15x.

The figure below shows the internal power system of the OSD32MP15x with all the power connections between the PMIC and the power domains of the processor. This internal configuration makes it possible for OSD32MP15x to have a simple external power configuration circuit described in the Power Inputs and Outputs and the Pin Configuration figures.

 

As can be seen from the above figures, the OSD32MP15x provides several output power rails. Some of them power the internal subsystems of the SiP and are purely test points on the boundary of the SiP and some of them are available for devices on board external to the SiP. The table below shows the voltage output levels of each of the voltage sources. All VOUTx and LDOx output voltages can be changed dynamically using I2C commands when the PMIC is in active mode. If you wish to change these voltages, you must reprogram the BUCKS_VOUT_SHR (VOUTx) and LDOS_VOUT_SHRx (LDOx) registers in the PMIC non-volatile memory (NVM). The process is detailed in the PMIC Reprogramming Application Note and ST’s PMIC programming guide.

The following legend shows the configuration options of each of the output power rails according to the color coding of their row in the Power Output Configuration table:

PMIC Features and Functions

Power up/Power Down Sequence

The default power-up/power down sequence of the PMIC is shown in the table below.

The order in which output power rails are activated is determined by Rank. Automatically, Rank1 powers up first, Rank2 powers up second, and Rank3 powers up last. However, Power rails with Rank0 do not power up automatically, and must be enabled after the device has booted using the PMIC I2C interface.

Turn-ON Conditions

The Turn-ON condition in the Power-up/Power-down Sequence figure refers to one of the following:

1. PONKEYn pin detection (falling edge)
2. VBUS detection (voltage on VBUSOTG or SWOUT above VBUSOTG_Rise or SWOUT_Rise, respectively. These conditions can be disabled.)
3. WAKEUP pin detection (rising edge)

The Auto turn-ON feature of the STPMIC1A allows it to transition to the POWER_ON state if VIN rises above VINOK_Rise. See the VIN Threshold table and the STPMIC1A State Machine diagram for more information.

Turn-OFF Conditions

The Turn-OFF condition in the Power-up/Power-down Sequence figure refers to one of the following:

1. Software switch OFF with SWOFF bit in MAIN_CR register of the PMIC
2. PONKEYn long press
3. Thermal shutdown
4. Overcurrent protection
5. Watchdog timer expiration
6. VIN falls below VIN_OK_Fall (See the VIN Threshold table for more information)

The Turn-OFF feature of the STPMIC1A allows it to transition to the OFF state. See the STPMIC1A State Machine diagram for more information.

VIN Thresholds

To trigger certain PMIC events, like Turn-ON and Turn-OFF conditions, the voltage of the VIN power input must rise above or fall below certain voltage thresholds. The following figure shows the different threshold triggers of STPMIC1A:

 

The four thresholds that most affect customer applications are: VIN_POR_Rise, VIN_POR_Fall, VINOK_Rise and VINOK_Fall. The table below provides the definitions and specifications for these thresholds for the OSD32MP15x device which uses the STPMIC1A.

For more details on the different power states, see the STPMIC1A State Machine diagram.

Efficiencies of Power Rails

The table below shows the minimum efficiencies of the BUCK and BOOST converters of STPMC1A inside the OSD32MP15x. These efficiencies can be helpful in accurately determining the total power consumption of the board during power budgeting. Note that the efficiency listed is the minimum efficiency of the power rail. This efficiency is used to calculate a worst-case power scenario for all the converters.

LDO Dropout Voltages

The table below shows the maximum dropout voltages for each of the four programmable LDOs of OSD32MP15x. These dropout voltages must be considered when setting the output voltages of these LDOs in the kernel device tree. For LDO2 and LDO5, the input voltage is provided externally through PMIC_LDO25IN. For LDO1 and LDO6, the input voltage is provided by PMIC_VOUT4. Therefore, the output voltage of each LDO must be less than the input voltage minus the dropout voltage. For example, if PMIC_VOUT4 is configured to be 3.3V, then the maximum voltage of LDO1 and LDO6 is 3.0V.

STPMIC1A State Machine

The PMIC has a fixed start up and power down sequence described by a state machine. The figure below shows the state machine diagram for STPMIC1A.

To better understand each state, a description is provided in the following table.

Some important points to be aware of for the OSD32MP15x:

1. By default, VINOK_Rise threshold is set to 3.5V. It can be changed by modifying the NVM of the PMIC. See the VIN Thresholds section for more information.
2. By default, the AUTO_TURN_ON bit in the NVM of STPMIC1A is set to 1. So, the PMIC proceeds to the CHECK&LOAD state immediately after PRELOAD_NVM.
3. Turn-ON conditions are listed in Turn-ON Conditions section.
4. Turn-OFF conditions are listed in Turn-OFF Conditions sections.

For more information, see Section 5.2 of STPMIC1A Datasheet.

Conclusion

This document discussed the power management system of OSD32MP15x and its many features. If you have other questions, please visit our forums.

Revision History

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