[gil_he]

hello Neeraj,

1. According to STM32CubeProgrammer data, it supports debug through ST-LINK debug probe (JTAG).
I know the PMIC doesn’t have a JTAG interface, but it connects through I2C4 to the STM SOC, and that allows the SOC access to the PMIC NVM.
That is my path to the PMIC NVM. The STM32CubeProgrammer uses this path to access and program this NVM (via JTAG).
Am I correct?
Does using JTAG require BOOTn=100 or does the JTAG anyway takes control once a debug probe is connected at power up?

2. I see I2C4 is accessed through APB5 bus which is accessed by the AHB bus master, M4.
The DAP (JTAG/SWD) is accessed via the DAP bus which connects to M4.
Is that why M4 is being used for accessing the NVM?
The DAP (JTAG/SWD) is also accessed by the AXI bus master, A7.
Am I correct?
Is the STM32CubeProgramme JTAG access transparent to the user, or should I take ay design measures to support that?

3. Programming the PMIC NVM procedure:
– Allowing the system to power up fully.
– Either by an I2C header or STM32CubeProgrammer (via JTAG):
disable VDD3V3_USBHS (PMIC LDO4).
change VDD (BUCK3) to 1.8V
– VDDA1V8_REG gets 1.8V as an input (internally). Its output is not regulated but will not cause any damage or affects MTBF of the SIP. Is that correct?
– Power off. Connecting BYPASS_REG1V8 pin to VDD and connecting VDD externally to VDDA1V8_REG pin.
– Power on.
Is the procedure ok?

thanks
Gil

[gil_he]

Hi Neeraj,

In addition to the above, if I hold NRST low and PMIC outputs are disabled, VDD (BUCK3) will also be disabled, thus I will not have VIO which is mandatory for PMIC NVM programming (VIO is connected to VDD internally in the SIP).

This is the first power-up of the SIP. Later power-ups will not need to do that.
1. BYPASS_REG1V8 is connected to GND.
VDDA1V8_REG is floating.
2. The system powers up.
3. Now, I am looking for a mechanism/method to do the following in the PMIC: disable VDD3V3_USBHS, change VDD (BUCK3) to 1.8V in the PMIC NVM.
How do you suggest I do that?
I can use an I2C header as described in dm00682242-the-stpmic1-ic-programming-guide-stmicroelectronics.pdf and program the PMIC NVM externally.
I can connect through JTAG to the SIP and access/program the PMIC NVM – is that feasible?
Any other way? What do you think?
4. Once VDD is changed to 1.8V in the NVM, I am powering the system off. Connecting BYPASS_REG1V8 and VDDA1V8_REG to VDD (resistors).
From now on, all power-ups are according to the PMIC NVM.

thanks
Gil

[gil_he]

Hi Neeraj,

When connecting to the SIP through JTAG:
Can the NVM of the PMIC be programmed via JTAG?
Which SW can be used for that?

thanks
Gil

• This reply was modified 2 years, 11 months ago by gil_he.

[gil_he]

Hi Neeraj,

The situation I described is for a board with the SiP assembled on it.
Default BUCK3 voltage is 3.3V (on first power-up, before any programming) and the connections on the board are as I described (BYPASS_REG1V8 and VDDA1V8_REG pins connect to VDD=3.3V).
So, it will put VDDA1V8_REG in bypass mode and will connect 3.3V (on first power-up), through the VDDA1V8_REG pin, to the USB HS PHY, which is wrong (it should get 1.8V).

Will the guide you referred me to, answer this scenario?

thanks
Gil

• This reply was modified 2 years, 11 months ago by gil_he.

[gil_he]

hello,

Please ignore the first post on this thread and consider the following (I edited the post, but something went wrong):

We will be using the OSD32MP157C-512M-BAA.
The default voltage for BUCK3 and BUCK4 is 3.3V.
I want to change it to 1.8V.
In the design, BYPASS_REG1V8 and VDDA1V8_REG pins connect to VDD, and will get 1.8V.
This is correct for a VDD=1.8V.
However, on first power-up of the system, 3.3V will be present there by default.
This will put VDDA1V8_REG in bypass mode and will connect 3.3V (through the VDDA1V8_REG pin) to the USB HS PHY, which is wrong.

How should I handle this?
BYPASS_REG1V8 will connect to VDD, thus in bypass mode.
VDDA1V8_REG pin will be floating. Thus, VDDA1V8_REG is not powered and USB PLL (in USB HS PHY) will not be get its 1.8V.
VDD3V3_USBHS will be disabled on power-up by default (fulfil the “VDDA1V8_REG must be present before VDD3V3_USBHS” requirement)
BUCK3 will change to 1.8V through the STM and once it is 1.8V, connect VDD to VDDA1V8_REG pin (either power-down the system and do that, or electrically relay VDD to this pin).
Enable VDD3V3_USBHS and change its power-up state to the appropriate rank.

Is that a valid way?

Any better way to do that?

thanks
Gil

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