[kiwisdr]

Thanks Greg. I’ll be sending a contact form reply soon. Need to do a little more research first.

[kiwisdr]

Greg,

If you guys want to set the world on fire you should consider a SiP using the low-end Xilinx Zynq 7z007s FPGA / Cortex-A9 SoC. Although this part is fairly new it seems to be available in decent retail quantities and I’d bet you’d have no problems getting dice from Xilinx. And probably full backing from Xilinx marketing as well. It would be a huge win for them in their eternal battle against Altera/Intel (translation: easier for you to negotiate better than the $46 retail price).

Now this is obviously a huge departure from what you’ve been doing. But the philosophy remains the same. The worst problems for us as FPGA/SoC developers are the routing of the DDRx memory interface and the multi-voltage requirement pushing us into 6-layer (or more) PCBs. If you put a 512 MB DDR3L and one of the many FPGA-specific PMICs in the SiP that would be enough (same as you do now). It’s easy these days to deal with external USB, Ethernet PHY, SDIO etc as you are well aware.

There are lots of challenges of course. The die size will determine the difficulty. The 7z007s already has limited I/O pins for the SoC peripherals and you wouldn’t want to make that situation any worse. I’d trade a larger SiP package to get all the I/Os. Your packaging will effect the high-end performance of the FPGA I/Os. But for a low-end device most people aren’t so worried about that I would think. For example my application is limited to about 70 MHz.

• This reply was modified 6 years, 1 month ago by kiwisdr.

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