[Aedan Cullen]

<p id=”docs-internal-guid-70e29185-7fff-97b0-0d38-c39dbf26df72″ dir=”ltr”>Awesome, I’m glad you got it working. I think the reason you can’t directly set &dma2 in the device tree is that DMAMUX configuration is needed to route the request signal from DCMI to DMA2 within the SoC, and that remains unconfigured if the device tree only references the DMA controller directly. You could potentially try changing only the SPI TX DMA to &dma2 to see if that’ll still work since the CPU is starting the transfer – I didn’t yet look closely to see whether it should.
<p dir=”ltr”>In the stm32-dmamux.c driver, it definitely seems to be an oversight that there is no provision for manually choosing a controller. They just take the 16 total channels (eight DMA0 followed by eight DMA1) and assign them sequentially as you saw. I think ST may not have anticipated/tested DMA use for simultaneous video streams like this. The cleanest approach I can think of right now would be to improve the stm32-dmamux.c driver to add (optional) manual multiplexing control in the device tree.

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