SPI bus performance

[gil_he]

hello,

On the OSD32MP153C, I need to use two SPI buses and I need those that will give me the highest bandwidth/performance.
One SPI interface will be Master and another one will be Slave.
SW running on the A7 (under Linux) will handle these interfaces and the data on them.

As far as SPI clock goes, I found that:
SPI1 Master 80MHz
SPI1 Slave 100MHz
SPI2/3 Master/Slave 100MHz
SPI4/5/6 Master/Slave 66MHz

SPI6 connects through APB5 (133MHz) to the AXIM bus (A7 cores).
SPI1-SPI5 connect through APB1/2 (104.5MHz) to MLAHB (M4 bus, 209MHz) and then the AXIM bus (A7 cores).

From “shortest path to A7 cores” point of view, SPI6 seems the preferred interface.
From “SPI clock frequency” point of view, SPI2/3 as Master and SPI1 as Slave are the preferred interfaces.

Please advise:
When summing up all the factors, which bus will give the highest performance? (descending order, fastest first).

Thank you!
Gil

[Neeraj Dantu]

Gil,

From the shortest path point of view, according to the reference manual, SPI2/3 seem to be the closest as MPU connected to them via AHB-APB1. According to https://www.st.com/content/ccc/resource/training/technical/product_training/group0/6c/56/80/c9/e2/1b/40/db/STM32MP1-Peripheral-Serial_Peripheral_interface_SPI/files/STM32MP1-Peripheral-Serial_Peripheral_interface_SPI.pdf/_jcr_content/translations/en.STM32MP1-Peripheral-Serial_Peripheral_interface_SPI.pdf, SPI2/3 seem to be interfaces that can achieve maximum frequency. Please make sure you can set the clock speeds you need using CubeMX clock tree utility.

Best,
Neeraj

[gil_he]

Hi Neeraj,

SPI2/3 are connected to the MPU via AHB-APB1, but the MPU is not planned to be used in our application.
As I wrote, the A7 cores will handle the SPI communication (through the driver that will run under Linux).

so, taking into account that the SPI data should reach the A7 cores and the speeds of the SPI interfaces, which SPI bus should I use?

Also, you wrote “Please make sure you can set the clock speeds you need using CubeMX clock tree utility”.
Any reason why it will not be possible to do that using that utility?

thanks
Gil

[Neeraj Dantu]

Gil,

I just realized I am wrong. You are correct. SPI6 is closest to A7 cores for latency purposes. All the other SPIs would have similar latencies.

Note that there are 4 PLLs available for the whole SoC and generate all the frequencies required for all the peripherals. For example, SPI6 can have one or the following clock sources: PCLk5, PLL4Q, PLL3Q, HSI, CSI and HSE. These can also serve as clock sources for other peripherals.

Best,
Neeraj

[gil_he]

Hi Neeraj,

Should that be a consideration when choosing the SPI interface?
Do other SPI interfaces have less or more clock sources than SPI6 has?
Is the flexibility, of choosing a clock source, different between SPI interfaces?

thanks
Gil

[Neeraj Dantu]

Gil,

I recommend you start a design in STM32CubeMX(https://www.st.com/en/development-tools/stm32cubemx.html) and look at the “Clock tree” section to understand all the constraints you will face while clocking your interfaces. You can browse example projects like STM32MP157C-DK2 to see how a reference clock tree is implemented.

Best,
Neeraj

[gil_he]

Hi Neeraj,

I will look into the constraints when defining the resources for the SPI interfaces.
I chose SPI1 and SPI2 for my design (HW pins wise) and intend to operate them in the maximum BW (100MHz clock).
Any possibility I will not be able to clock them correctly?

thanks
Gil

[Neeraj Dantu]

Gil,

I was able to set frequencies for them on CubeMX without issue via PLL3. You should be good, but please make sure you are okay with the clock tree in CubeMX.

Best,
Neeraj

[gil_he]

Very well.
thank you!

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