PMIC Power Down Behavior

[Simon Acker]

Good afternoon!

I am verifying a PCBA design with an OSD3358-512M-ICB C-SIP. It is my understanding that the power down sequence should be the reverse of the power up sequence. There are a handful of places where the power down sequence of our design does not match what I’d expect. I would be grateful for clarification on whether we should be concerned about these variations from the expected behavior. Thanks!

1. PMIC_PGOOD, PMIC_NWAKEUP, and PMIC_LDO_PGOOD drop-out behavior. During power-down, these three signals are briefly pulled low before decaying as expected. While not clear in these first scope capture, the drop-out behavior occurs simultaneously for all three signals. It almost looks like these external pins are briefly disconnected. In our design, these signals are connected exactly how they are in the OSM33558-C-SIP-RED reference design.

2. VDDSHV_3P3V and SYS_VDD1_3P3V begin to fall ~3.6 ms before VDD_CORE and VDD_MPU begin to fall. Based on the reverse power-up sequence, I would expect VDD_CORE and VDD_MPU to begin to fall about 1 ms before VDDSHV_3P3V and SYS_VDD1_3P3V. Our design for all of these signals match the design with the exception that VDDSHV2 is connected to SYS_VDD_1P8V instead of SYS_VDD3_3P3V like the rest of the VDDSHV pins.

 

 

[Neeraj Dantu]

Simon,

I cannot see the pictures you posted, not sure why. Here are some inputs based on your description:

On #1, These are digital IO of the PMIC, not sure if there is an issue with them going Low during power down.

On #2, can you check your PMIC registers, specifically 0x19 – 0x1E(see https://www.ti.com/lit/ds/symlink/tps65217.pdf) and make sure they correspond to ‘C’ version of the PMIC?

You can go through support if you are facing issues including/attaching images.

Best,

Neeraj

[Simon Acker]

Hi Neeraj,

I just confirmed that registers 0x19-0x1E match the reset values for the ‘C’ version of the PMIC.

Best,

Simon

[Simon Acker]

Here are those scope captures. I tried the file attachment rather than copy paste. Hopefully that works better.

Attachments:

1. 

   Scope-Capture-1.png
   

2. 

   Scope-Capture-2.png
   

3. 

   Scope-Capture-3.png
   

[Simon Acker]

Resolved. I was causing a sudden power off. These issues go away when the “poweroff” command is used. This command uses the processor’s RTC to cause PMIC_PWR_EN to go low after a brief delay. Pulling PMIC_PWR_EN low is the proper power down sequence.

[Neeraj Dantu]

Simon,

Appreciate the update. Thanks!

Best,

Neeraj

[Simon Acker]

Hi Neeraj,

Upon further investigation of the controlled power down behavior, we are seeing a bump in the power down waveform for SYS_VDD3_3P3V. I’ve attached a scope capture. We’ve powered VDDSHV 1 & 3-6 with SYS_VDD3_3P3V, so SYS_VDD3_3P3V is labelled VDDSHV_3V3 in the scope capture below. In addition to the VDDSHV connections, SYS_VDD3_3P3V is also connected to a clamping circuit identical to the reference design for the C-SIP and an analog pin (to measure its voltage).

As I understand it, the VDDSHV voltages can be used as the pull-up for various GPIO pins. A similar bump is visible on a couple of inputs where the external driver (pull-up) was removed. I’ve attached a scope capture of one (OCT_EMMC_PG) below. I was able to suppress the bump with a 510 ohm resistor but not with a weaker one. These two factors indicate to me that this bump is driven.

Have you seen this behavior before? Is it concerning? Will it damage the device?

Thanks,

Simon

Attachments:

1. 

   Picture1.png
   

2. 

   MicrosoftTeams-image.png
   

[Neeraj Dantu]

Simon,

The first thing to check would be if there is a back current on VDDSHV/SYS_VDD3_3P3V. This can happen if the IO of the processor are being driven/pulled-up by an external device that is still being powered after the PMIC power rails have come down. Please take a look at the power down sequencing of the PMIC in relation to the power down sequencing of the rest of the board.

Best,

Neeraj

[Simon Acker]

Resolved. We had the Octavo connected to an ethernet switch via an RGMII connection. The ethernet switch remained powered when the Octavo was off. The powered ethernet switch continued to provide a clock waveform via the RX_CLK signal of the RGMII connection. This clock waveform was causing the bump discussed previously. It was also causing SYS_VDD3_3V3 and SYS_VDD1_3V3 to read non-zero voltages (1V & 0.5V, respectively) when the PMIC was off.

Thanks for your help Neeraj!

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