automated power up/power down sequencing

[memaher]

Sorry, this is a very general question as I’m trying to figure it out in my head.

Assuming my system is sitting isolated with no operator intevention, I need it to:
1. automatically power up when 5v is provided to it
– this is generally straight forward using a reset supervisor
2. automatically power down when 5v is removed
– this is the more interesting of the problems

So, I guess the fundemental questions are:
a. can the standard battery source be used to prop the system up long enough to power down?
b. any ideas on how to notify of power fail – can the PMIC signal the processor, or is this best done with external logic?
c. how to configure the OS to drop everytihng and power down?

Can’t believe this hasn’t already been done, but haven’t found anything yet!

Mat

[Eshtaartha Basu]

Hello memaher,

a. can the standard battery source be used to prop the system up long enough to power down?

The TPS65217C PMIC used in OSD335x family of devices supports 1S Li-ion/Li-polymer battery. The battery life depends on the average power consumption figures for your specific design and the capacity (mAh value) of the battery chosen. In general, a 1S battery would be able to power the OSD335x long enough for shutdown.

b. any ideas on how to notify of power fail – can the PMIC signal the processor, or is this best done with external logic?
The PMIC considers the VIN_BAT input as one of its primary power inputs. VIN_BAT is not considered as a backup input. Hence, PMIC will not signal the processor when it switches from VIN_AC/VIN_USB to VIN_BAT. However, you can use an external logic to assert the power button (PMIC_PB_IN) when VIN_AC fails. MSP430FR2xxx Ultra Low Power MCU can be a good fit for low power external control logic.

c. how to configure the OS to drop everytihng and power down?
You can do this by asserting the power button (PMIC_PB_IN) through an external logic. When the power button is pressed, an interrupt is sent to the processor by the PMIC. The BeagleBoard.org and RED Debian images facilitate an orderly shutdown (by default) by saving files and un-mounting drives once they receive this interrupt. Keep in mind that this is not an instant shutdown. The system will take a while to shutdown. However, you could modify how Linux interprets the interrupt from the PMIC by making suitable software modifications.

[memaher]

good suggestions. I followed them by putting an MSP430 as power/reset supervisor coupling to a supercap bank. Calculations show this should provide enough power to keep the system alive long enough to perform shutdown.

However, one problem I’ve got is knowing when the processor is actually shutdown. Of course the default response would be to wait for PMIC_PGOOD to fall, but this may be a very long time after the processor has departed. Reading a GPIO is the next best thing, but any application driving this will get removed before shutdown.

Can you think of any way to detect the moment of powerdown?

[Neeraj Dantu]

memaher,

Just like the power up sequencing, there is a shutdown power sequencing when the system shuts down. By default, this sequence follows the reverse order of the power-up sequence(see section 8.3.1.2 of PMIC datasheet: http://www.ti.com/lit/ds/symlink/tps65217.pdf). For specific power up sequence for TPS65217C see section 10 in this application note: http://www.ti.com/lit/ug/slvu551i/slvu551i.pdf.

As you can see from the above documents, the first two steps of the power up sequence are that the PWR_EN which is an input to the PMIC is asserted after RTC subsystem is powered. In a power down sequence, PWR_EN would be pulled low by the processor after which SYS_RTC_1P8V would go down.  So, PMIC_POWER_EN(N10) can be monitored to know when the processor is de-asserting this signal to know when the shutdown has occurred. As this is the last action that will be taken by the processor, this would be the moment of powerdown as you describe it.

Best,

Neeraj

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