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Pin Mapping between OSDZU3 and the XCZU3

Published On: December, 15, 2023 By: Erik Welsh

This document is a quick reference to understand the mapping of the pins between the OSDZU3 Family of devices, and the XCZU3 processor.  The Pin Map Charts are sortable by both XCZU3 discrete device as well as OSDZU3 system in package.

There are a couple of high level differences between the OSDZU3 and the XCZU3 that are helpful to understand when using this document:
1. The OSDZU3 integrates the DDR. Therefore all DDR related pins are not pinned out on the XCZU3.
2. Mapping sorted by Discrete Device and Signal Names.

An Excel Workbook containing these tables and others can be downloaded here.

These tables have multiple pages.  Each column can be sorted using the arrows in the column header.  they can be searched by using the respective search box.

OSDZU3 to Discrete Mapping

OSDZU3 Pin NameOSDZU3 Pin NumberDiscrete DeviceDiscrete Device Signal NameDiscrete Device Pin NumberComments
DXNA19XCZU3DXNU12Temperature sensing diode pin
DXPB19XCZU3DXPU13Temperature sensing diode pin
VSSA1ALLGND(1)
VSSA26ALLGND(1)
VSSA29ALLGND(1)
VSSA30ALLGND(1)
VSSB1ALLGND(1)
VSSB25ALLGND(1)
VSSB27ALLGND(1)
VSSB28ALLGND(1)
VSSC26ALLGND(1)
VSSC29ALLGND(1)
VSSC30ALLGND(1)
VSSD25ALLGND(1)
VSSD27ALLGND(1)
VSSD28ALLGND(1)
VSSE26ALLGND(1)
VSSE29ALLGND(1)
VSSE30ALLGND(1)
VSSF27ALLGND(1)
VSSF28ALLGND(1)
VSSG10ALLGND(1)
VSSG11ALLGND(1)
VSSG12ALLGND(1)
VSSG13ALLGND(1)
VSSG17ALLGND(1)
VSSG18ALLGND(1)
VSSG19ALLGND(1)
VSSG26ALLGND(1)
VSSG29ALLGND(1)
VSSG30ALLGND(1)
VSSG7ALLGND(1)
VSSG8ALLGND(1)
VSSG9ALLGND(1)
VSSH10ALLGND(1)
VSSH11ALLGND(1)
VSSH12ALLGND(1)
VSSH13ALLGND(1)
VSSH14ALLGND(1)
VSSH17ALLGND(1)
VSSH18ALLGND(1)
VSSH19ALLGND(1)
VSSH20ALLGND(1)
VSSH21ALLGND(1)
VSSH25ALLGND(1)
VSSH27ALLGND(1)
VSSH28ALLGND(1)
VSSH7ALLGND(1)
VSSJ11ALLGND(1)
VSSJ12ALLGND(1)
VSSJ13ALLGND(1)
VSSJ14ALLGND(1)
VSSJ15ALLGND(1)
VSSJ16ALLGND(1)
VSSJ17ALLGND(1)
VSSJ18ALLGND(1)
VSSJ20ALLGND(1)
VSSJ21ALLGND(1)
VSSJ26ALLGND(1)
VSSJ29ALLGND(1)
VSSJ30ALLGND(1)
VSSJ7ALLGND(1)
VSSK11ALLGND(1)
VSSK12ALLGND(1)
VSSK13ALLGND(1)
VSSK14ALLGND(1)
VSSK15ALLGND(1)
VSSK16ALLGND(1)
VSSK17ALLGND(1)
VSSK18ALLGND(1)
VSSK20ALLGND(1)
VSSK21ALLGND(1)
VSSK22ALLGND(1)
VSSK23ALLGND(1)
VSSK24ALLGND(1)
VSSK25ALLGND(1)
VSSK27ALLGND(1)
VSSK28ALLGND(1)
VSSK7ALLGND(1)
VSSL12ALLGND(1)
VSSL14ALLGND(1)
VSSL15ALLGND(1)
VSSL16ALLGND(1)
VSSL18ALLGND(1)
VSSL20ALLGND(1)
VSSL22ALLGND(1)
VSSL23ALLGND(1)
VSSL24ALLGND(1)
VSSL26ALLGND(1)
VSSL29ALLGND(1)
VSSL30ALLGND(1)
VSSL7ALLGND(1)
VSSM12ALLGND(1)
VSSM14ALLGND(1)
VSSM15ALLGND(1)
VSSM18ALLGND(1)
VSSM19ALLGND(1)
VSSM20ALLGND(1)
VSSM23ALLGND(1)
VSSM24ALLGND(1)
VSSM25ALLGND(1)
VSSM27ALLGND(1)
VSSM28ALLGND(1)
VSSM7ALLGND(1)
VSSN11ALLGND(1)
VSSN12ALLGND(1)
VSSN13ALLGND(1)
VSSN15ALLGND(1)
VSSN16ALLGND(1)
VSSN17ALLGND(1)
VSSN21ALLGND(1)
VSSN22ALLGND(1)
VSSN26ALLGND(1)
VSSN29ALLGND(1)
VSSN30ALLGND(1)
VSSN7ALLGND(1)
VSSP10ALLGND(1)
VSSP11ALLGND(1)
VSSP12ALLGND(1)
VSSP13ALLGND(1)
VSSP7ALLGND(1)
VSSP8ALLGND(1)
VSSP9ALLGND(1)
VSSW1ALLGND(1)
VSSW28ALLGND(1)
VSSW29ALLGND(1)
VSSW30ALLGND(1)
VSSY1ALLGND(1)
VSSY28ALLGND(1)
GND_PSADCY30XCZU3GND_PSADCW20
GNDADCA23XCZU3GNDADCP13
GNDADCB22XCZU3GNDADCP13
GNDADCB23XCZU3GNDADCP13
GNDADCC23XCZU3GNDADCP13
GNDADCD22XCZU3GNDADCP13
24N_L10T18XCZU3IO_L10N_AD10N_24Y13
25N_L10C11XCZU3IO_L10N_AD10N_25A10
26N_L10F16XCZU3IO_L10N_AD2N_26H13
44N_L10R12XCZU3IO_L10N_AD2N_44Y10
64N_L10Y8XCZU3IO_L10N_T1U_N7_QBC_AD4N_64AG5
65N_L10K4XCZU3IO_L10N_T1U_N7_QBC_AD4N_65H3
66N_L10B3XCZU3IO_L10N_T1U_N7_QBC_AD4N_66A4
24P_L10T17XCZU3IO_L10P_AD10P_24Y14
25P_L10B11XCZU3IO_L10P_AD10P_25B11
26P_L10F15XCZU3IO_L10P_AD2P_26H14
44P_L10R11XCZU3IO_L10P_AD2P_44W10
64P_L10W8XCZU3IO_L10P_T1U_N6_QBC_AD4P_64AG6
65P_L10J4XCZU3IO_L10P_T1U_N6_QBC_AD4P_65H4
66P_L10A3XCZU3IO_L10P_T1U_N6_QBC_AD4P_66B4
26N_L11E19XCZU3IO_L11N_AD1N_26J14
44N_L11R14XCZU3IO_L11N_AD1N_44AA8
24N_L11R16XCZU3IO_L11N_AD9N_24W11
25N_L11A13XCZU3IO_L11N_AD9N_25A11
64N_L11T10XCZU3IO_L11N_T1U_N9_GC_64AF6
65N_L11M4XCZU3IO_L11N_T1U_N9_GC_65K3
66N_L11D4XCZU3IO_L11N_T1U_N9_GC_66C4
26P_L11E18XCZU3IO_L11P_AD1P_26K14
44P_L11R13XCZU3IO_L11P_AD1P_44Y9
24P_L11R15XCZU3IO_L11P_AD9P_24W12
25P_L11A12XCZU3IO_L11P_AD9P_25A12
64P_L11R10XCZU3IO_L11P_T1U_N8_GC_64AF7
65P_L11L4XCZU3IO_L11P_T1U_N8_GC_65K4
66P_L11C4XCZU3IO_L11P_T1U_N8_GC_66D4
26N_L12F18XCZU3IO_L12N_AD0N_26L13
44N_L12T14XCZU3IO_L12N_AD0N_44AB9
24N_L12T16XCZU3IO_L12N_AD8N_24AA12
25N_L12B13XCZU3IO_L12N_AD8N_25C12
64N_L12V10XCZU3IO_L12N_T1U_N11_GC_64AF5
65N_L12R2XCZU3IO_L12N_T1U_N11_GC_65L2
66N_L12E2XCZU3IO_L12N_T1U_N11_GC_66C2
26P_L12F17XCZU3IO_L12P_AD0P_26L14
44P_L12T13XCZU3IO_L12P_AD0P_44AB10
24P_L12T15XCZU3IO_L12P_AD8P_24Y12
25P_L12B12XCZU3IO_L12P_AD8P_25D12
64P_L12U10XCZU3IO_L12P_T1U_N10_GC_64AE5
65P_L12P2XCZU3IO_L12P_T1U_N10_GC_65L3
66P_L12D2XCZU3IO_L12P_T1U_N10_GC_66C3
64N_L13V7XCZU3IO_L13N_T2L_N1_GC_QBC_64AD4
65N_L13H5XCZU3IO_L13N_T2L_N1_GC_QBC_65L6
66N_L13B8XCZU3IO_L13N_T2L_N1_GC_QBC_66D6
64P_L13U7XCZU3IO_L13P_T2L_N0_GC_QBC_64AD5
65P_L13G5XCZU3IO_L13P_T2L_N0_GC_QBC_65L7
66P_L13A8XCZU3IO_L13P_T2L_N0_GC_QBC_66D7
64N_L14V5XCZU3IO_L14N_T2L_N3_GC_64AC3
65N_L14F5XCZU3IO_L14N_T2L_N3_GC_65L5
66N_L14F4XCZU3IO_L14N_T2L_N3_GC_66D5
64P_L14U5XCZU3IO_L14P_T2L_N2_GC_64AC4
65P_L14E5XCZU3IO_L14P_T2L_N2_GC_65M6
66P_L14E4XCZU3IO_L14P_T2L_N2_GC_66E5
64N_L15V6XCZU3IO_L15N_T2L_N5_AD11N_64AB3
65N_L15T4XCZU3IO_L15N_T2L_N5_AD11N_65N6
66N_L15D8XCZU3IO_L15N_T2L_N5_AD11N_66F6
64P_L15U6XCZU3IO_L15P_T2L_N4_AD11P_64AB4
65P_L15R4XCZU3IO_L15P_T2L_N4_AD11P_65N7
66P_L15C8XCZU3IO_L15P_T2L_N4_AD11P_66G6
64N_L16W2XCZU3IO_L16N_T2U_N7_QBC_AD3N_64AD1
65N_L16V4XCZU3IO_L16N_T2U_N7_QBC_AD3N_65P6
66N_L16F10XCZU3IO_L16N_T2U_N7_QBC_AD3N_66F7
64P_L16V2XCZU3IO_L16P_T2U_N6_QBC_AD3P_64AD2
65P_L16U4XCZU3IO_L16P_T2U_N6_QBC_AD3P_65P7
66P_L16E10XCZU3IO_L16P_T2U_N6_QBC_AD3P_66G8
64N_L17U2XCZU3IO_L17N_T2U_N9_AD10N_64AC2
65N_L17K6XCZU3IO_L17N_T2U_N9_AD10N_65N8
66N_L17D10XCZU3IO_L17N_T2U_N9_AD10N_66E8
64P_L17T2XCZU3IO_L17P_T2U_N8_AD10P_64AB2
65P_L17J6XCZU3IO_L17P_T2U_N8_AD10P_65N9
66P_L17C10XCZU3IO_L17P_T2U_N8_AD10P_66F8
64N_L18T1XCZU3IO_L18N_T2U_N11_AD2N_64AC1
65N_L18H6XCZU3IO_L18N_T2U_N11_AD2N_65L8
66N_L18B10XCZU3IO_L18N_T2U_N11_AD2N_66D9
64P_L18R1XCZU3IO_L18P_T2U_N10_AD2P_64AB1
65P_L18G6XCZU3IO_L18P_T2U_N10_AD2P_65M8
66P_L18A10XCZU3IO_L18P_T2U_N10_AD2P_66E9
64N_L19Y7XCZU3IO_L19N_T3L_N1_DBC_AD9N_64AH4
65N_L19B6XCZU3IO_L19N_T3L_N1_DBC_AD9N_65J4
66N_L19B4XCZU3IO_L19N_T3L_N1_DBC_AD9N_66A5
64P_L19W7XCZU3IO_L19P_T3L_N0_DBC_AD9P_64AG4
65P_L19A6XCZU3IO_L19P_T3L_N0_DBC_AD9P_65J5
66P_L19A4XCZU3IO_L19P_T3L_N0_DBC_AD9P_66B5
26N_L1A17XCZU3IO_L1N_AD11N_26A15
44N_L1Y13XCZU3IO_L1N_AD11N_44AH10
24N_L1W19XCZU3IO_L1N_AD15N_24AE14
25N_L1F12XCZU3IO_L1N_AD15N_25J10
64N_L1V9XCZU3IO_L1N_T0L_N1_DBC_64AD9
65N_L1T6XCZU3IO_L1N_T0L_N1_DBC_65Y8
66N_L1K1XCZU3IO_L1N_T0L_N1_DBC_66F1
26P_L1A16XCZU3IO_L1P_AD11P_26B15
44P_L1Y12XCZU3IO_L1P_AD11P_44AG10
24P_L1W18XCZU3IO_L1P_AD15P_24AE15
25P_L1F11XCZU3IO_L1P_AD15P_25J11
64P_L1U9XCZU3IO_L1P_T0L_N0_DBC_64AC9
65P_L1R6XCZU3IO_L1P_T0L_N0_DBC_65W8
66P_L1J1XCZU3IO_L1P_T0L_N0_DBC_66G1
64N_L20Y6XCZU3IO_L20N_T3L_N3_AD1N_64AH3
65N_L20F8XCZU3IO_L20N_T3L_N3_AD1N_65H6
66N_L20F7XCZU3IO_L20N_T3L_N3_AD1N_66B6
64P_L20W6XCZU3IO_L20P_T3L_N2_AD1P_64AG3
65P_L20E8XCZU3IO_L20P_T3L_N2_AD1P_65J6
66P_L20E7XCZU3IO_L20P_T3L_N2_AD1P_66C6
64N_L21Y5XCZU3IO_L21N_T3L_N5_AD8N_64AF3
65N_L21D5XCZU3IO_L21N_T3L_N5_AD8N_65H7
66N_L21B7XCZU3IO_L21N_T3L_N5_AD8N_66A6
64P_L21W5XCZU3IO_L21P_T3L_N4_AD8P_64AE3
65P_L21C5XCZU3IO_L21P_T3L_N4_AD8P_65J7
66P_L21A7XCZU3IO_L21P_T3L_N4_AD8P_66A7
64N_L22Y4XCZU3IO_L22N_T3U_N7_DBC_AD0N_64AF2
65N_L22P4XCZU3IO_L22N_T3U_N7_DBC_AD0N_65K7
66N_L22F9XCZU3IO_L22N_T3U_N7_DBC_AD0N_66B8
64P_L22W4XCZU3IO_L22P_T3U_N6_DBC_AD0P_64AE2
65P_L22N4XCZU3IO_L22P_T3U_N6_DBC_AD0P_65K8
66P_L22E9XCZU3IO_L22P_T3U_N6_DBC_AD0P_66C8
64N_L23Y3XCZU3IO_L23N_T3U_N9_64AH1
65N_L23F6XCZU3IO_L23N_T3U_N9_65J9
66N_L23B9XCZU3IO_L23N_T3U_N9_66A8
64P_L23W3XCZU3IO_L23P_T3U_N8_64AH2
66P_L23A9XCZU3IO_L23P_T3U_N8_66A9
65P_L23E6XCZU3IO_L23P_T3U_N8_I2C_SCLK_65K9
64N_L24V1XCZU3IO_L24N_T3U_N11_64AG1
66N_L24D9XCZU3IO_L24N_T3U_N11_66B9
65N_L24D6XCZU3IO_L24N_T3U_N11_PERSTN0_65H8
64P_L24U1XCZU3IO_L24P_T3U_N10_64AF1
66P_L24C9XCZU3IO_L24P_T3U_N10_66C9
65P_L24C6XCZU3IO_L24P_T3U_N10_PERSTN1_I2C_SDA_65H9
26N_L2B15XCZU3IO_L2N_AD10N_26A14
44N_L2W15XCZU3IO_L2N_AD10N_44AG11
24N_L2Y19XCZU3IO_L2N_AD14N_24AH14
25N_L2F14XCZU3IO_L2N_AD14N_25K12
64N_L2V11XCZU3IO_L2N_T0L_N3_64AE8
65N_L2T5XCZU3IO_L2N_T0L_N3_65V9
66N_L2H1XCZU3IO_L2N_T0L_N3_66D1
26P_L2B14XCZU3IO_L2P_AD10P_26B14
44P_L2W14XCZU3IO_L2P_AD10P_44AF11
24P_L2Y18XCZU3IO_L2P_AD14P_24AG14
25P_L2F13XCZU3IO_L2P_AD14P_25K13
64P_L2U11XCZU3IO_L2P_T0L_N2_64AE9
65P_L2R5XCZU3IO_L2P_T0L_N2_65U9
66P_L2G1XCZU3IO_L2P_T0L_N2_66E1
24N_L3Y17XCZU3IO_L3N_AD13N_24AH13
25N_L3E13XCZU3IO_L3N_AD13N_25G10
26N_L3A15XCZU3IO_L3N_AD9N_26A13
44N_L3Y15XCZU3IO_L3N_AD9N_44AH11
64N_L3T9XCZU3IO_L3N_T0L_N5_AD15N_64AC8
65N_L3P6XCZU3IO_L3N_T0L_N5_AD15N_65V8
66N_L3L2XCZU3IO_L3N_T0L_N5_AD15N_66E2
24P_L3Y16XCZU3IO_L3P_AD13P_24AG13
25P_L3E12XCZU3IO_L3P_AD13P_25H11
26P_L3A14XCZU3IO_L3P_AD9P_26B13
44P_L3Y14XCZU3IO_L3P_AD9P_44AH12
64P_L3R9XCZU3IO_L3P_T0L_N4_AD15P_64AB8
65P_L3N6XCZU3IO_L3P_T0L_N4_AD15P_65U8
66P_L3K2XCZU3IO_L3P_T0L_N4_AD15P_66F2
24N_L4W17XCZU3IO_L4N_AD12N_24AF13
25N_L4D13XCZU3IO_L4N_AD12N_25H12
26N_L4B17XCZU3IO_L4N_AD8N_26C13
44N_L4W13XCZU3IO_L4N_AD8N_44AF10
64N_L4V8XCZU3IO_L4N_T0U_N7_DBC_AD7N_64AE7
65N_L4P5XCZU3IO_L4N_T0U_N7_DBC_AD7N_65T8
66N_L4J2XCZU3IO_L4N_T0U_N7_DBC_AD7N_66F3
24P_L4W16XCZU3IO_L4P_AD12P_24AE13
25P_L4D12XCZU3IO_L4P_AD12P_25J12
26P_L4B16XCZU3IO_L4P_AD8P_26C14
44P_L4W12XCZU3IO_L4P_AD8P_44AE10
64P_L4U8XCZU3IO_L4P_T0U_N6_DBC_AD7P_64AD7
66P_L4H2XCZU3IO_L4P_T0U_N6_DBC_AD7P_66G3
65P_L4N5XCZU3IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65R8
24N_L5V19XCZU3IO_L5N_HDGC_24AD14
25N_L5C13XCZU3IO_L5N_HDGC_25F10
26N_L5C17XCZU3IO_L5N_HDGC_AD7N_26D14
44N_L5V15XCZU3IO_L5N_HDGC_AD7N_44AF12
64N_L5T8XCZU3IO_L5N_T0U_N9_AD14N_64AC7
65N_L5M6XCZU3IO_L5N_T0U_N9_AD14N_65T7
66N_L5G2XCZU3IO_L5N_T0U_N9_AD14N_66E3
24P_L5V18XCZU3IO_L5P_HDGC_24AD15
25P_L5C12XCZU3IO_L5P_HDGC_25G11
26P_L5C16XCZU3IO_L5P_HDGC_AD7P_26D15
44P_L5V14XCZU3IO_L5P_HDGC_AD7P_44AE12
64P_L5R8XCZU3IO_L5P_T0U_N8_AD14P_64AB7
65P_L5L6XCZU3IO_L5P_T0U_N8_AD14P_65R7
66P_L5F2XCZU3IO_L5P_T0U_N8_AD14P_66E4
24N_L6V17XCZU3IO_L6N_HDGC_24AC13
25N_L6D15XCZU3IO_L6N_HDGC_25F11
26N_L6D17XCZU3IO_L6N_HDGC_AD6N_26E13
44N_L6U15XCZU3IO_L6N_HDGC_AD6N_44AD12
64N_L6T7XCZU3IO_L6N_T0U_N11_AD6N_64AC6
65N_L6M5XCZU3IO_L6N_T0U_N11_AD6N_65T6
66N_L6H4XCZU3IO_L6N_T0U_N11_AD6N_66F5
24P_L6V16XCZU3IO_L6P_HDGC_24AC14
25P_L6D14XCZU3IO_L6P_HDGC_25F12
26P_L6D16XCZU3IO_L6P_HDGC_AD6P_26E14
44P_L6U14XCZU3IO_L6P_HDGC_AD6P_44AC12
64P_L6R7XCZU3IO_L6P_T0U_N10_AD6P_64AB6
65P_L6L5XCZU3IO_L6P_T0U_N10_AD6P_65R6
66P_L6G4XCZU3IO_L6P_T0U_N10_AD6P_66G5
24N_L7U17XCZU3IO_L7N_HDGC_24AB13
25N_L7E15XCZU3IO_L7N_HDGC_25D10
26N_L7C19XCZU3IO_L7N_HDGC_AD5N_26F13
44N_L7V13XCZU3IO_L7N_HDGC_AD5N_44AD10
64N_L7Y11XCZU3IO_L7N_T1L_N1_QBC_AD13N_64AH9
65N_L7P1XCZU3IO_L7N_T1L_N1_QBC_AD13N_65K1
66N_L7F1XCZU3IO_L7N_T1L_N1_QBC_AD13N_66B1
24P_L7U16XCZU3IO_L7P_HDGC_24AA13
25P_L7E14XCZU3IO_L7P_HDGC_25E10
26P_L7C18XCZU3IO_L7P_HDGC_AD5P_26G13
44P_L7V12XCZU3IO_L7P_HDGC_AD5P_44AD11
64P_L7W11XCZU3IO_L7P_T1L_N0_QBC_AD13P_64AG9
65P_L7N1XCZU3IO_L7P_T1L_N0_QBC_AD13P_65L1
66P_L7E1XCZU3IO_L7P_T1L_N0_QBC_AD13P_66C1
24N_L8U19XCZU3IO_L8N_HDGC_24AB14
25N_L8C15XCZU3IO_L8N_HDGC_25D11
26N_L8D19XCZU3IO_L8N_HDGC_AD4N_26E15
44N_L8U13XCZU3IO_L8N_HDGC_AD4N_44AC11
64N_L8Y9XCZU3IO_L8N_T1L_N3_AD5N_64AG8
65N_L8M1XCZU3IO_L8N_T1L_N3_AD5N_65H1
66N_L8D1XCZU3IO_L8N_T1L_N3_AD5N_66A1
24P_L8U18XCZU3IO_L8P_HDGC_24AB15
25P_L8C14XCZU3IO_L8P_HDGC_25E12
26P_L8D18XCZU3IO_L8P_HDGC_AD4P_26F15
44P_L8U12XCZU3IO_L8P_HDGC_AD4P_44AB11
64P_L8W9XCZU3IO_L8P_T1L_N2_AD5P_64AF8
65P_L8L1XCZU3IO_L8P_T1L_N2_AD5P_65J1
66P_L8C1XCZU3IO_L8P_T1L_N2_AD5P_66A2
24N_L9R18XCZU3IO_L9N_AD11N_24W13
25N_L9E11XCZU3IO_L9N_AD11N_25B10
26N_L9E17XCZU3IO_L9N_AD3N_26G14
44N_L9T12XCZU3IO_L9N_AD3N_44AA10
64N_L9Y10XCZU3IO_L9N_T1L_N5_AD12N_64AH7
65N_L9N2XCZU3IO_L9N_T1L_N5_AD12N_65J2
66N_L9C2XCZU3IO_L9N_T1L_N5_AD12N_66A3
24P_L9R17XCZU3IO_L9P_AD11P_24W14
25P_L9D11XCZU3IO_L9P_AD11P_25C11
26P_L9E16XCZU3IO_L9P_AD3P_26G15
44P_L9T11XCZU3IO_L9P_AD3P_44AA11
64P_L9W10XCZU3IO_L9P_T1L_N4_AD12P_64AH8
65P_L9M2XCZU3IO_L9P_T1L_N4_AD12P_65K2
66P_L9B2XCZU3IO_L9P_T1L_N4_AD12P_66B3
64_T0J5XCZU3IO_T0U_N12_VRP_64AD6
65_T0P3XCZU3IO_T0U_N12_VRP_65W9
66_T0F3XCZU3IO_T0U_N12_VRP_66G4
64_T1V3XCZU3IO_T1U_N12_64AH6
65_T1G3XCZU3IO_T1U_N12_65H2
66_T1C3XCZU3IO_T1U_N12_66D2
64_T2R3XCZU3IO_T2U_N12_64AB5
65_T2B5XCZU3IO_T2U_N12_65P9
66_T2D7XCZU3IO_T2U_N12_66E7
64_T3K5XCZU3IO_T3U_N12_64AE4
65_T3A5XCZU3IO_T3U_N12_65K5
66_T3C7XCZU3IO_T3U_N12_66C7
+3V3_ONN24PMICNot connected to the ZU3N/APowered by LDO1. Powers EEPROM.
+3V3_ONP24PMICNot connected to the ZU3N/APowered by LDO1. Powers EEPROM.
+5V_INH8PMICNot Connected to the ZU3N/APower Input to OSDZU3 Device
+5V_INH9PMICNot Connected to the ZU3N/APower Input to OSDZU3 Device
+5V_INJ8PMICNot Connected to the ZU3N/APower Input to OSDZU3 Device
+5V_INJ9PMICNot Connected to the ZU3N/APower Input to OSDZU3 Device
+5V_INK8PMICNot Connected to the ZU3N/APower Input to OSDZU3 Device
+5V_INK9PMICNot Connected to the ZU3N/APower Input to OSDZU3 Device
+5V_INL8PMICNot Connected to the ZU3N/APower Input to OSDZU3 Device
+5V_INL9PMICNot Connected to the ZU3N/APower Input to OSDZU3 Device
+5V_INM8PMICNot Connected to the ZU3N/APower Input to OSDZU3 Device
+5V_INM9PMICNot Connected to the ZU3N/APower Input to OSDZU3 Device
+5V_INN8PMICNot Connected to the ZU3N/APower Input to OSDZU3 Device
+5V_INN9PMICNot Connected to the ZU3N/APower Input to OSDZU3 Device
PMIC2_CJ10PMICNot connected to the ZU3N/APowered by PMIC2 VOUT_C
PMIC2_CK10PMICNot connected to the ZU3N/APowered by PMIC2 VOUT_C
PMIC2_CL10PMICNot connected to the ZU3N/APowered by PMIC2 VOUT_C
PMIC2_CM10PMICNot connected to the ZU3N/APowered by PMIC2 VOUT_C
VSUPPLYN10PMICNot Connected to the ZU3N/APower Input to OSDZU3 Device
EEPROM_WPN27EEPROMNot connected to ZU3N/AEEPROM write protect. Internally pulled up to +3V3_ON to enable Write Protect to EEPROM by default. Connect to GND to disable write protect.
GND_ANAA2PMICNot connected to ZU3N/APMIC analog GND
GND_ANAY2PMICNot connected to ZU3N/APMIC analog GND
OSC_OEF25OSCILLATORNot connected to ZU3N/A33MHz Oscillator enable. Internally pulled up to VCC_PSAUX to enable 33MHz oscillator
PGOODJ3PMICNot connected to ZU3N/APMIC1 and PMIC2 Power Good output indicating proper operation of all power rails
PMIC_IRQBK3PMICNot connected to ZU3N/APMIC1/2 Alert# line. Pulled up to VDDIO through 10K resistor.
PMIC_SCLP27PMICNot connected to ZU3N/AConnected to I2C of PMIC1/2 and EEPROM
PMIC_SDAR27PMICNot connected to ZU3N/AConnected to I2C of PMIC1/2 and EEPROM
PMIC_SLEEPT3PMICNot connected to ZU3N/APMIC1/2 sleep mode control, +3V3_ON LDO enable pin, internally pulled up to +5V_IN
PMIC1_BG14PMICNot connected to ZU3N/AExternal use. Powered by PMIC1 VOUT_B
PMIC1_BP15PMICNot connected to ZU3N/AExternal use. Powered by PMIC1 VOUT_B
PMIC1_MTPU3PMICNot connected to ZU3N/ATie to GND through a 2.32Kohm Resistor for default operation
PMIC2_MTPD3PMICNot connected to ZU3N/ATie to GND through a 2.87Kohm Resistor for default operation
PWR_ENH3PMICNot connected to Zu3N/APMIC1/2 power rails enable pin. Internally pulled up to +3V3_ON
RSVDA11N/ANot connected to ZU3N/AReserved for future use. Do not connect (2)
RSVDE3N/ANot connected to ZU3N/AReserved for future use. Do not connect (2)
RSVDL19N/ANot connected to ZU3N/AReserved for future use. Do not connect (2)
RSVDM16N/ANot connected to ZU3N/AReserved for future use. Do not connect (2)
RSVDM17N/ANot connected to ZU3N/AReserved for future use. Do not connect (2)
RSVDM21N/ANot connected to ZU3N/AReserved for future use. Do not connect (2)
RSVDM22N/ANot connected to ZU3N/AReserved for future use. Do not connect (2)
RSVDN18N/ANot connected to ZU3N/AReserved for future use. Do not connect (2)
RSVDN19N/ANot connected to ZU3N/AReserved for future use. Do not connect (2)
RSVDN20N/ANot connected to ZU3N/AReserved for future use. Do not connect (2)
RSVDP16N/ANot connected to ZU3N/AReserved for future use. Do not connect (2)
RSVDP17N/ANot connected to ZU3N/AReserved for future use. Do not connect (2)
RSVDP21N/ANot connected to ZU3N/AReserved for future use. Do not connect (2)
RSVDP22N/ANot connected to ZU3N/AReserved for future use. Do not connect (2)
RSVDW27N/ANot connected to ZU3N/AReserved for future use. Do not connect (2)
RSVDY27N/ANot connected to ZU3N/AReserved for future use. Do not connect (2)
VDDION3XCZU3Not connected to ZU3N/APMIC1/2 IO control voltage, MUST be connected to a 3.3V power source to set 3.3V I2C interface
POR_OVERRIDEJ22XCZU3POR_OVERRIDEW7Power on reset delay override. Pulled low to GND to set standard PL power on delay time
PS_DONEN28XCZU3PS_DONEM21Indicates the PS configuration is completed
PS_ERR_OUTL3XCZU3PS_ERROR_OUTP17Asserted for accidental loss of power, a hardware error, or an exception in the PMU
PS_ERR_STATM3XCZU3PS_ERROR_STATUSM20Indicates a secure lockdown state. Alternatively, it can be used by the PMU firmware to indicate system status
PS_INIT_BP29XCZU3PS_INIT_BP21Indicates the PL is initialized after a power-on reset (POR). This signal should not be held Low externally to delay the PL configuration sequence because the signal level is not visible to software. However, if there is a CRC error detected when the PL bit stream is loaded PS_INIT_B will be driven low
PS_TCKT30XCZU3PS_JTAG_TCKR19JTAG
PS_TDIR29XCZU3PS_JTAG_TDIR18JTAG
PS_TDOR30XCZU3PS_JTAG_TDOT21JTAG
PS_TMSR28XCZU3PS_JTAG_TMSN21JTAG
+MGTRAVCCK26XCZU3PS_MGTRAVCCB22, D22Powered by LDO2. Test point for internal power supply for GTRs
+MGTRAVTTM26XCZU3PS_MGTRAVTTA23, C23, D25, E23Powered by PMIC1 VO_LDO. Test point for internal power supply for GTRs
GTR_CLK_N0L28XCZU3PS_MGTREFCLK0N_505F24GTR Lane 0
GTR_CLK_P0L27XCZU3PS_MGTREFCLK0P_505F23GTR Lane 0
GTR_CLK_N1H30XCZU3PS_MGTREFCLK1N_505E22GTR Lane 1
GTR_CLK_P1H29XCZU3PS_MGTREFCLK1P_505E21GTR Lane 1
GTR_CLK_N2E28XCZU3PS_MGTREFCLK2N_505C22GTR Lane 2
GTR_CLK_P2E27XCZU3PS_MGTREFCLK2P_505C21GTR Lane 2
GTR_CLK_N3B30XCZU3PS_MGTREFCLK3N_505A22GTR Lane 3
GTR_CLK_P3B29XCZU3PS_MGTREFCLK3P_505A21GTR Lane 3
PS_MGTRREFH26XCZU3PS_MGTRREF_505F22Calibration resistor pin for the termination resistor calibration circuit for the PS-GTR transceivers. Needs to be connected externally. See Schematic Checklist
GTR_RX_N0K30XCZU3PS_MGTRRXN0_505F28GTR Lane 0
GTR_RX_N1J28XCZU3PS_MGTRRXN1_505D28GTR Lane 1
GTR_RX_N2D30XCZU3PS_MGTRRXN2_505B28GTR Lane 2
GTR_RX_N3C28XCZU3PS_MGTRRXN3_505A26GTR Lane 3
GTR_RX_P0K29XCZU3PS_MGTRRXP0_505F27GTR Lane 0
GTR_RX_P1J27XCZU3PS_MGTRRXP1_505D27GTR Lane 1
GTR_RX_P2D29XCZU3PS_MGTRRXP2_505B27GTR Lane 2
GTR_RX_P3C27XCZU3PS_MGTRRXP3_505A25GTR Lane 3
GTR_TX_N0M30XCZU3PS_MGTRTXN0_505E26GTR Lane 0
GTR_TX_N1G28XCZU3PS_MGTRTXN1_505D24GTR Lane 1
GTR_TX_N2F30XCZU3PS_MGTRTXN2_505C26GTR Lane 2
GTR_TX_N3A28XCZU3PS_MGTRTXN3_505B24GTR Lane 3
GTR_TX_P0M29XCZU3PS_MGTRTXP0_505E25GTR Lane 0
GTR_TX_P1G27XCZU3PS_MGTRTXP1_505D23GTR Lane 1
GTR_TX_P2F29XCZU3PS_MGTRTXP2_505C25GTR Lane 2
GTR_TX_P3A27XCZU3PS_MGTRTXP3_505B23GTR Lane 3
MIO0W20XCZU3PS_MIO0AG15
MIO1W21XCZU3PS_MIO1AG16
MIO10Y25XCZU3PS_MIO10AD17
MIO11V24XCZU3PS_MIO11AE17
MIO12W25XCZU3PS_MIO12AC17
MIO13Y22XCZU3PS_MIO13AH18
MIO14Y23XCZU3PS_MIO14AG18
MIO15W24XCZU3PS_MIO15AE18
MIO16Y24XCZU3PS_MIO16AF18
MIO17W26XCZU3PS_MIO17AC18
MIO18V28XCZU3PS_MIO18AC19
MIO19Y26XCZU3PS_MIO19AE19
MIO2V20XCZU3PS_MIO2AF15
MIO20V27XCZU3PS_MIO20AD19
MIO21V30XCZU3PS_MIO21AC21
MIO22V29XCZU3PS_MIO22AB20
MIO23V25XCZU3PS_MIO23AB18
MIO24V26XCZU3PS_MIO24AB19
MIO25U30XCZU3PS_MIO25AB21
MIO26U21XCZU3PS_MIO26L15
MIO27T20XCZU3PS_MIO27J15
MIO28U20XCZU3PS_MIO28K15
MIO29T19XCZU3PS_MIO29G16
MIO3Y20XCZU3PS_MIO3AH15
MIO30R19XCZU3PS_MIO30F16
MIO31R20XCZU3PS_MIO31H16
MIO32T21XCZU3PS_MIO32J16
MIO33U22XCZU3PS_MIO33L16
MIO34U23XCZU3PS_MIO34L17
MIO35R21XCZU3PS_MIO35H17
MIO36T23XCZU3PS_MIO36K17
MIO37T22XCZU3PS_MIO37J17
MIO38R22XCZU3PS_MIO38H18
MIO39R23XCZU3PS_MIO39H19
MIO4Y21XCZU3PS_MIO4AH16
MIO40T24XCZU3PS_MIO40K18
MIO41R24XCZU3PS_MIO41J19
MIO42U24XCZU3PS_MIO42L18
MIO43U25XCZU3PS_MIO43K19
MIO44T25XCZU3PS_MIO44J20
MIO45T27XCZU3PS_MIO45K20
MIO46T26XCZU3PS_MIO46L20
MIO47U26XCZU3PS_MIO47H21
MIO48T28XCZU3PS_MIO48J21
MIO49U28XCZU3PS_MIO49M18
MIO5W23XCZU3PS_MIO5AD16
MIO50U29XCZU3PS_MIO50M19
MIO51U27XCZU3PS_MIO51L21
MIO52P25XCZU3PS_MIO52G18
MIO53F20XCZU3PS_MIO53D16
MIO54F21XCZU3PS_MIO54F17
MIO55E20XCZU3PS_MIO55B16
MIO56F19XCZU3PS_MIO56C16
MIO57D20XCZU3PS_MIO57A16
MIO58L25XCZU3PS_MIO58F18
MIO59E21XCZU3PS_MIO59E17
MIO6V21XCZU3PS_MIO6AF16
MIO60E22XCZU3PS_MIO60C17
MIO61F22XCZU3PS_MIO61D17
MIO62D23XCZU3PS_MIO62A17
MIO63F23XCZU3PS_MIO63E18
MIO64F24XCZU3PS_MIO64E19
MIO65A24XCZU3PS_MIO65A18
MIO66R25XCZU3PS_MIO66G19
MIO67B24XCZU3PS_MIO67B18
MIO68D24XCZU3PS_MIO68C18
MIO69E23XCZU3PS_MIO69D19
MIO7W22XCZU3PS_MIO7AH17
MIO70C24XCZU3PS_MIO70C19
MIO71C25XCZU3PS_MIO71B19
MIO72P26XCZU3PS_MIO72G20
MIO73R26XCZU3PS_MIO73G21
MIO74E24XCZU3PS_MIO74D20
MIO75A25XCZU3PS_MIO75A19
MIO76E25XCZU3PS_MIO76B20
MIO77N25XCZU3PS_MIO77F20
MIO8V22XCZU3PS_MIO8AF17
MIO9V23XCZU3PS_MIO9AC16
PS_MODE0G23XCZU3PS_MODE0P194-bit boot mode pins sampled on POR de-assertion
PS_MODE1G24XCZU3PS_MODE1P204-bit boot mode pins sampled on POR de-assertion
PS_MODE2J23XCZU3PS_MODE2R204-bit boot mode pins sampled on POR de-assertion
PS_MODE3J24XCZU3PS_MODE3T204-bit boot mode pins sampled on POR de-assertion
PS_PADID26XCZU3PS_PADIN17Crystal pad input (RTC) 10 Mohm resistor required to be placed between PS_PADI and PS_PADO to use the RTC
PS_PADOF26XCZU3PS_PADON18Crystal pad input (RTC) 10 Mohm resistor required to be placed between PS_PADI and PS_PADO to use the RTC
PS_POR_BP30XCZU3PS_POR_BP16Power-on reset signal (connected internally to PGOOD)
PS_PROG_BP28XCZU3PS_PROG_BR17PS configuration reset signal
PS_REF_CLKB26XCZU3PS_REF_CLKR16System reference clock connected to the output of internal 33MHz oscillator
PS_SRST_BT29XCZU3PS_SRST_BN19System reset commonly used during debug
PUDC_BH22XCZU3PUDC_BU7Active low input to enable internal pull-ups during configuration on all SelectIO pins. Pin pulled to VCCAUX to disable Weak preconfiguration I/O pull-up resistors
VCC_PSADCY29XCZU3VCC_PSADCY20PS SYSMON ADC supply voltage
VCC_PSAUXH24XCZU3VCC_PSAUXU19, U20, V19, W19Powered by PMIC2 VOUT_A
VCC_PSAUXN23XCZU3VCC_PSAUXU19, U20, V19, W19Powered by PMIC2 VOUT_A
VCC_PSBATTA18XCZU3VCC_PSBATTY18Battery Input
VCC_PSDDR_PLLB18XCZU3VCC_PSDDR_PLLU16, U18Need to be Connected externally. See Schematic checklist
VCC_PSINTFPJ19XCZU3VCC_PSINTFP, VCC_PSINTFP_DDRAA15, AA16, AA17, AA18, AB16, Y15, Y17, AA20, AA21, Y19Powered by PMIC2 VOUT_D
VCC_PSINTFPK19XCZU3VCC_PSINTFP, VCC_PSINTFP_DDRAA15, AA16, AA17, AA18, AB16, Y15, Y17, AA20, AA21, Y19Powered by PMIC2 VOUT_D
VCC_PSINTLPL13XCZU3VCC_PSINTLPV16, V17, V18, W15, W16, W17Powered by PMIC2 VOUT_B
VCC_PSINTLPM13XCZU3VCC_PSINTLPV16, V17, V18, W15, W16, W17Powered by PMIC2 VOUT_B
VCC_PSPLLL17XCZU3VCC_PSPLLT16, T17, T18Powered by PMIC2 VO_LDO
VCCADCA20XCZU3VCCADCP12PL System Monitor supply
VCCADCB20XCZU3VCCADCP12PL System Monitor supply
VCCADCB21XCZU3VCCADCP12PL System Monitor supply
VCCADCC20XCZU3VCCADCP12PL System Monitor supply
VCCADCD21XCZU3VCCADCP12PL System Monitor supply
VCCAUXG22XCZU3VCCAUX, VCCAUX_IOM16, N16, M13, M14, M15Powered by PMIC1 VOUT_A
VCCAUXP19XCZU3VCCAUX, VCCAUX_IOM16, N16, M13, M14, M15Powered by PMIC1 VOUT_A
VCCINTL11XCZU3VCCINT, VCCINT_IO, VCCBRAMN11, N13, N15, P10, P14, P15, R10, R11, R14, T11, T15, U10, U14, U15, V10, V11, V12, V14, K10, L10, M10, M9, L11, L12, M11, M12Powered by PMIC1 VOUT_D
VCCINTM11XCZU3VCCINT, VCCINT_IO, VCCBRAMN11, N13, N15, P10, P14, P15, R10, R11, R14, T11, T15, U10, U14, U15, V10, V11, V12, V14, K10, L10, M10, M9, L11, L12, M11, M12Powered by PMIC1 VOUT_D
VCCO_HDIO_24P20XCZU3VCCO_24AA14, AD13Need to be Connected externally. See Schematic checklist
VCCO_HDIO_25G20XCZU3VCCO_25B12, E11Need to be Connected externally. See Schematic Checklist
VCCO_HDIO_26G21XCZU3VCCO_26C15, F14Need to be Connected externally. See Schematic Checklist
VCCO_HDIO_44P18XCZU3VCCO_44AC10, AG12Need to be Connected externally. See Schematic Checklist
VCCO_HPIO_64P14XCZU3VCCO_64AC5, AD8, AG7Need to be Connected externally. See Schematic Checklist
VCCO_HPIO_65G15XCZU3VCCO_65H5, J3, L4Need to be Connected externally. See Schematic Checklist
VCCO_HPIO_66G16XCZU3VCCO_66B7, D3, E6Need to be Connected externally. See Schematic Checklist
VCCO_PSDDRL21XCZU3VCCO_PSDDRAB22, AD23, AF24, P23, T24, V25, Y26Powered by PMIC1 VOUT_C. Only used as a test point
VCCO_PSIO_500P23XCZU3VCCO_PSIO0_500AB17, AE16, AG17Need to be Connected externally. Should be connected to either 1.8V or 3.3V depending on the version of the device. See Schematic checklist.
VCCO_PSIO_501J25XCZU3VCCO_PSIO1_501H20, L19Need to be Connected externally. See Schematic Checklist
VCCO_PSIO_502G25XCZU3VCCO_PSIO2_502D18, G17Need to be Connected externally. See Schematic Checklist
VCCO_PSIO_503H23XCZU3VCCO_PSIO3_503M17, P18Need to be Connected externally. See Schematic Checklist
VNA22XCZU3VNT12System Monitor dedicated differential analog input. Should be tied to GNDADC if unused
VPA21XCZU3VPR13System Monitor dedicated differential analog input. Should be tied to GNDADC if unused
VREF_64N14XCZU3VREF_64AA7Need to be Connected externally. See Schematic Checklist
VREF_65H15XCZU3VREF_65R9Need to be Connected externally. See Schematic Checklist
VREF_66H16XCZU3VREF_66G9Need to be Connected externally. See Schematic Checklist
VREFNC22XCZU3VREFNR12Voltage reference GND
VREFPC21XCZU3VREFPT13Voltage reference input

 

Notes:

(1)See GND pin in XCZU3 DatasheetA20, A24, A27, A28, AA1, AA19, AA2, AA24, AA3, AA4, AA5, AA6, AA9, AB12, AB27, AC15, AC20, AC25, AD18, AD3, AE1, AE11, AE21, AE26, AE6, AF14, AF19, AF4, AF9, AG2, AG22, AG27, AH5, B17, B2, B21, B25,B26, C10, C20, C24, C27, C28, C5, D13, D21, D26, D8, E16, E20, E24, E27, E28, F19, F21, F25, F26, F4, F9, G12, G2, G22, G23, G24, G27, G28, G7, H10, H15, H25, J13, J18, J23, J8, K11, K16, K21, K26, K6, L24, L9, M1, M2, M22, M27, M3, M4, M5, M7, N10, N12, N14, N20, N25, N5, P11, P3, P5, P8, R1, R15, R2, R21, R26, R5, T10, T14, T19, T3, T5, T9, U1, U11, U17, U2, U22, U27, U6, V13, V15, V3, V7, W1, W18, W2, W23, W6, Y11, Y16, Y3, Y7
(2)See NC pin in XCZU3 DatasheetN1, N2, N3, N4, P1, P2, P4, R3, R4, T1, T2, T4, U21, U3, U4, U5, V1, V2, V20, V21, V4, V5, V6, W21, W3, W4, W5, Y1, Y2, Y21, Y4, Y5, Y6

 

Discrete to OSDZU3 Mapping

Discrete DeviceDiscrete Signal NameDiscrete Pin NumberSiP Signal NameSiP PinsNotes
XCZU3DXN U12 DXNA19Temperature sensing diode pin
XCZU3DXP U13 DXPB19Temperature sensing diode pin
XCZU3GND A20 VSS(1)
XCZU3GND A24 VSS(1)
XCZU3GND A27 VSS(1)
XCZU3GND A28 VSS(1)
XCZU3GND AA1 VSS(1)
XCZU3GND AA19 VSS(1)
XCZU3GND AA2 VSS(1)
XCZU3GND AA24 VSS(1)
XCZU3GND AA3 VSS(1)
XCZU3GND AA4 VSS(1)
XCZU3GND AA5 VSS(1)
XCZU3GND AA6 VSS(1)
XCZU3GND AA9 VSS(1)
XCZU3GND AB12 VSS(1)
XCZU3GND AB27 VSS(1)
XCZU3GND AC15 VSS(1)
XCZU3GND AC20 VSS(1)
XCZU3GND AC25 VSS(1)
XCZU3GND AD18 VSS(1)
XCZU3GND AD3 VSS(1)
XCZU3GND AE1 VSS(1)
XCZU3GND AE11 VSS(1)
XCZU3GND AE21 VSS(1)
XCZU3GND AE26 VSS(1)
XCZU3GND AE6 VSS(1)
XCZU3GND AF14 VSS(1)
XCZU3GND AF19 VSS(1)
XCZU3GND AF4 VSS(1)
XCZU3GND AF9 VSS(1)
XCZU3GND AG2 VSS(1)
XCZU3GND AG22 VSS(1)
XCZU3GND AG27 VSS(1)
XCZU3GND AH5 VSS(1)
XCZU3GND B17 VSS(1)
XCZU3GND B2 VSS(1)
XCZU3GND B21 VSS(1)
XCZU3GND B25 VSS(1)
XCZU3GND B26 VSS(1)
XCZU3GND C10 VSS(1)
XCZU3GND C20 VSS(1)
XCZU3GND C24 VSS(1)
XCZU3GND C27 VSS(1)
XCZU3GND C28 VSS(1)
XCZU3GND C5 VSS(1)
XCZU3GND D13 VSS(1)
XCZU3GND D21 VSS(1)
XCZU3GND D26 VSS(1)
XCZU3GND D8 VSS(1)
XCZU3GND E16 VSS(1)
XCZU3GND E20 VSS(1)
XCZU3GND E24 VSS(1)
XCZU3GND E27 VSS(1)
XCZU3GND E28 VSS(1)
XCZU3GND F19 VSS(1)
XCZU3GND F21 VSS(1)
XCZU3GND F25 VSS(1)
XCZU3GND F26 VSS(1)
XCZU3GND F4 VSS(1)
XCZU3GND F9 VSS(1)
XCZU3GND G12 VSS(1)
XCZU3GND G2 VSS(1)
XCZU3GND G22 VSS(1)
XCZU3GND G23 VSS(1)
XCZU3GND G24 VSS(1)
XCZU3GND G27 VSS(1)
XCZU3GND G28 VSS(1)
XCZU3GND G7 VSS(1)
XCZU3GND H10 VSS(1)
XCZU3GND H15 VSS(1)
XCZU3GND H25 VSS(1)
XCZU3GND J13 VSS(1)
XCZU3GND J18 VSS(1)
XCZU3GND J23 VSS(1)
XCZU3GND J8 VSS(1)
XCZU3GND K11 VSS(1)
XCZU3GND K16 VSS(1)
XCZU3GND K21 VSS(1)
XCZU3GND K26 VSS(1)
XCZU3GND K6 VSS(1)
XCZU3GND L24 VSS(1)
XCZU3GND L9 VSS(1)
XCZU3GND M1 VSS(1)
XCZU3GND M2 VSS(1)
XCZU3GND M22 VSS(1)
XCZU3GND M27 VSS(1)
XCZU3GND M3 VSS(1)
XCZU3GND M4 VSS(1)
XCZU3GND M5 VSS(1)
XCZU3GND M7 VSS(1)
XCZU3GND N10 VSS(1)
XCZU3GND N12 VSS(1)
XCZU3GND N14 VSS(1)
XCZU3GND N20 VSS(1)
XCZU3GND N25 VSS(1)
XCZU3GND N5 VSS(1)
XCZU3GND P11 VSS(1)
XCZU3GND P3 VSS(1)
XCZU3GND P5 VSS(1)
XCZU3GND P8 VSS(1)
XCZU3GND R1 VSS(1)
XCZU3GND R15 VSS(1)
XCZU3GND R2 VSS(1)
XCZU3GND R21 VSS(1)
XCZU3GND R26 VSS(1)
XCZU3GND R5 VSS(1)
XCZU3GND T10 VSS(1)
XCZU3GND T14 VSS(1)
XCZU3GND T19 VSS(1)
XCZU3GND T3 VSS(1)
XCZU3GND T5 VSS(1)
XCZU3GND T9 VSS(1)
XCZU3GND U1 VSS(1)
XCZU3GND U11 VSS(1)
XCZU3GND U17 VSS(1)
XCZU3GND U2 VSS(1)
XCZU3GND U22 VSS(1)
XCZU3GND U27 VSS(1)
XCZU3GND U6 VSS(1)
XCZU3GND V13 VSS(1)
XCZU3GND V15 VSS(1)
XCZU3GND V3 VSS(1)
XCZU3GND V7 VSS(1)
XCZU3GND W1 VSS(1)
XCZU3GND W18 VSS(1)
XCZU3GND W2 VSS(1)
XCZU3GND W23 VSS(1)
XCZU3GND W6 VSS(1)
XCZU3GND Y11 VSS(1)
XCZU3GND Y16 VSS(1)
XCZU3GND Y3 VSS(1)
XCZU3GND Y7 VSS(1)
XCZU3GND_PSADC W20 GND_PSADCY30
XCZU3GNDADC P13 GNDADCA23, B22, B23, C23, D22
XCZU3IO_L10N_AD10N_24 Y13 24N_L10T18
XCZU3IO_L10N_AD10N_25 A10 25N_L10C11
XCZU3IO_L10N_AD2N_26 H13 26N_L10F16
XCZU3IO_L10N_AD2N_44 Y10 44N_L10R12
XCZU3IO_L10N_T1U_N7_QBC_AD4N_64 AG5 64N_L10Y8
XCZU3IO_L10N_T1U_N7_QBC_AD4N_65 H3 65N_L10K4
XCZU3IO_L10N_T1U_N7_QBC_AD4N_66 A4 66N_L10B3
XCZU3IO_L10P_AD10P_24 Y14 24P_L10T17
XCZU3IO_L10P_AD10P_25 B11 25P_L10B11
XCZU3IO_L10P_AD2P_26 H14 26P_L10F15
XCZU3IO_L10P_AD2P_44 W10 44P_L10R11
XCZU3IO_L10P_T1U_N6_QBC_AD4P_64 AG6 64P_L10W8
XCZU3IO_L10P_T1U_N6_QBC_AD4P_65 H4 65P_L10J4
XCZU3IO_L10P_T1U_N6_QBC_AD4P_66 B4 66P_L10A3
XCZU3IO_L11N_AD1N_26 J14 26N_L11E19
XCZU3IO_L11N_AD1N_44 AA8 44N_L11R14
XCZU3IO_L11N_AD9N_24 W11 24N_L11R16
XCZU3IO_L11N_AD9N_25 A11 25N_L11A13
XCZU3IO_L11N_T1U_N9_GC_64 AF6 64N_L11T10
XCZU3IO_L11N_T1U_N9_GC_65 K3 65N_L11M4
XCZU3IO_L11N_T1U_N9_GC_66 C4 66N_L11D4
XCZU3IO_L11P_AD1P_26 K14 26P_L11E18
XCZU3IO_L11P_AD1P_44 Y9 44P_L11R13
XCZU3IO_L11P_AD9P_24 W12 24P_L11R15
XCZU3IO_L11P_AD9P_25 A12 25P_L11A12
XCZU3IO_L11P_T1U_N8_GC_64 AF7 64P_L11R10
XCZU3IO_L11P_T1U_N8_GC_65 K4 65P_L11L4
XCZU3IO_L11P_T1U_N8_GC_66 D4 66P_L11C4
XCZU3IO_L12N_AD0N_26 L13 26N_L12F18
XCZU3IO_L12N_AD0N_44 AB9 44N_L12T14
XCZU3IO_L12N_AD8N_24 AA12 24N_L12T16
XCZU3IO_L12N_AD8N_25 C12 25N_L12B13
XCZU3IO_L12N_T1U_N11_GC_64 AF5 64N_L12V10
XCZU3IO_L12N_T1U_N11_GC_65 L2 65N_L12R2
XCZU3IO_L12N_T1U_N11_GC_66 C2 66N_L12E2
XCZU3IO_L12P_AD0P_26 L14 26P_L12F17
XCZU3IO_L12P_AD0P_44 AB10 44P_L12T13
XCZU3IO_L12P_AD8P_24 Y12 24P_L12T15
XCZU3IO_L12P_AD8P_25 D12 25P_L12B12
XCZU3IO_L12P_T1U_N10_GC_64 AE5 64P_L12U10
XCZU3IO_L12P_T1U_N10_GC_65 L3 65P_L12P2
XCZU3IO_L12P_T1U_N10_GC_66 C3 66P_L12D2
XCZU3IO_L13N_T2L_N1_GC_QBC_64 AD4 64N_L13V7
XCZU3IO_L13N_T2L_N1_GC_QBC_65 L6 65N_L13H5
XCZU3IO_L13N_T2L_N1_GC_QBC_66 D6 66N_L13B8
XCZU3IO_L13P_T2L_N0_GC_QBC_64 AD5 64P_L13U7
XCZU3IO_L13P_T2L_N0_GC_QBC_65 L7 65P_L13G5
XCZU3IO_L13P_T2L_N0_GC_QBC_66 D7 66P_L13A8
XCZU3IO_L14N_T2L_N3_GC_64 AC3 64N_L14V5
XCZU3IO_L14N_T2L_N3_GC_65 L5 65N_L14F5
XCZU3IO_L14N_T2L_N3_GC_66 D5 66N_L14F4
XCZU3IO_L14P_T2L_N2_GC_64 AC4 64P_L14U5
XCZU3IO_L14P_T2L_N2_GC_65 M6 65P_L14E5
XCZU3IO_L14P_T2L_N2_GC_66 E5 66P_L14E4
XCZU3IO_L15N_T2L_N5_AD11N_64 AB3 64N_L15V6
XCZU3IO_L15N_T2L_N5_AD11N_65 N6 65N_L15T4
XCZU3IO_L15N_T2L_N5_AD11N_66 F6 66N_L15D8
XCZU3IO_L15P_T2L_N4_AD11P_64 AB4 64P_L15U6
XCZU3IO_L15P_T2L_N4_AD11P_65 N7 65P_L15R4
XCZU3IO_L15P_T2L_N4_AD11P_66 G6 66P_L15C8
XCZU3IO_L16N_T2U_N7_QBC_AD3N_64 AD1 64N_L16W2
XCZU3IO_L16N_T2U_N7_QBC_AD3N_65 P6 65N_L16V4
XCZU3IO_L16N_T2U_N7_QBC_AD3N_66 F7 66N_L16F10
XCZU3IO_L16P_T2U_N6_QBC_AD3P_64 AD2 64P_L16V2
XCZU3IO_L16P_T2U_N6_QBC_AD3P_65 P7 65P_L16U4
XCZU3IO_L16P_T2U_N6_QBC_AD3P_66 G8 66P_L16E10
XCZU3IO_L17N_T2U_N9_AD10N_64 AC2 64N_L17U2
XCZU3IO_L17N_T2U_N9_AD10N_65 N8 65N_L17K6
XCZU3IO_L17N_T2U_N9_AD10N_66 E8 66N_L17D10
XCZU3IO_L17P_T2U_N8_AD10P_64 AB2 64P_L17T2
XCZU3IO_L17P_T2U_N8_AD10P_65 N9 65P_L17J6
XCZU3IO_L17P_T2U_N8_AD10P_66 F8 66P_L17C10
XCZU3IO_L18N_T2U_N11_AD2N_64 AC1 64N_L18T1
XCZU3IO_L18N_T2U_N11_AD2N_65 L8 65N_L18H6
XCZU3IO_L18N_T2U_N11_AD2N_66 D9 66N_L18B10
XCZU3IO_L18P_T2U_N10_AD2P_64 AB1 64P_L18R1
XCZU3IO_L18P_T2U_N10_AD2P_65 M8 65P_L18G6
XCZU3IO_L18P_T2U_N10_AD2P_66 E9 66P_L18A10
XCZU3IO_L19N_T3L_N1_DBC_AD9N_64 AH4 64N_L19Y7
XCZU3IO_L19N_T3L_N1_DBC_AD9N_65 J4 65N_L19B6
XCZU3IO_L19N_T3L_N1_DBC_AD9N_66 A5 66N_L19B4
XCZU3IO_L19P_T3L_N0_DBC_AD9P_64 AG4 64P_L19W7
XCZU3IO_L19P_T3L_N0_DBC_AD9P_65 J5 65P_L19A6
XCZU3IO_L19P_T3L_N0_DBC_AD9P_66 B5 66P_L19A4
XCZU3IO_L1N_AD11N_26 A15 26N_L1A17
XCZU3IO_L1N_AD11N_44 AH10 44N_L1Y13
XCZU3IO_L1N_AD15N_24 AE14 24N_L1W19
XCZU3IO_L1N_AD15N_25 J10 25N_L1F12
XCZU3IO_L1N_T0L_N1_DBC_64 AD9 64N_L1V9
XCZU3IO_L1N_T0L_N1_DBC_65 Y8 65N_L1T6
XCZU3IO_L1N_T0L_N1_DBC_66 F1 66N_L1K1
XCZU3IO_L1P_AD11P_26 B15 26P_L1A16
XCZU3IO_L1P_AD11P_44 AG10 44P_L1Y12
XCZU3IO_L1P_AD15P_24 AE15 24P_L1W18
XCZU3IO_L1P_AD15P_25 J11 25P_L1F11
XCZU3IO_L1P_T0L_N0_DBC_64 AC9 64P_L1U9
XCZU3IO_L1P_T0L_N0_DBC_65 W8 65P_L1R6
XCZU3IO_L1P_T0L_N0_DBC_66 G1 66P_L1J1
XCZU3IO_L20N_T3L_N3_AD1N_64 AH3 64N_L20Y6
XCZU3IO_L20N_T3L_N3_AD1N_65 H6 65N_L20F8
XCZU3IO_L20N_T3L_N3_AD1N_66 B6 66N_L20F7
XCZU3IO_L20P_T3L_N2_AD1P_64 AG3 64P_L20W6
XCZU3IO_L20P_T3L_N2_AD1P_65 J6 65P_L20E8
XCZU3IO_L20P_T3L_N2_AD1P_66 C6 66P_L20E7
XCZU3IO_L21N_T3L_N5_AD8N_64 AF3 64N_L21Y5
XCZU3IO_L21N_T3L_N5_AD8N_65 H7 65N_L21D5
XCZU3IO_L21N_T3L_N5_AD8N_66 A6 66N_L21B7
XCZU3IO_L21P_T3L_N4_AD8P_64 AE3 64P_L21W5
XCZU3IO_L21P_T3L_N4_AD8P_65 J7 65P_L21C5
XCZU3IO_L21P_T3L_N4_AD8P_66 A7 66P_L21A7
XCZU3IO_L22N_T3U_N7_DBC_AD0N_64 AF2 64N_L22Y4
XCZU3IO_L22N_T3U_N7_DBC_AD0N_65 K7 65N_L22P4
XCZU3IO_L22N_T3U_N7_DBC_AD0N_66 B8 66N_L22F9
XCZU3IO_L22P_T3U_N6_DBC_AD0P_64 AE2 64P_L22W4
XCZU3IO_L22P_T3U_N6_DBC_AD0P_65 K8 65P_L22N4
XCZU3IO_L22P_T3U_N6_DBC_AD0P_66 C8 66P_L22E9
XCZU3IO_L23N_T3U_N9_64 AH1 64N_L23Y3
XCZU3IO_L23N_T3U_N9_65 J9 65N_L23F6
XCZU3IO_L23N_T3U_N9_66 A8 66N_L23B9
XCZU3IO_L23P_T3U_N8_64 AH2 64P_L23W3
XCZU3IO_L23P_T3U_N8_66 A9 66P_L23A9
XCZU3IO_L23P_T3U_N8_I2C_SCLK_65 K9 65P_L23E6
XCZU3IO_L24N_T3U_N11_64 AG1 64N_L24V1
XCZU3IO_L24N_T3U_N11_66 B9 66N_L24D9
XCZU3IO_L24N_T3U_N11_PERSTN0_65 H8 65N_L24D6
XCZU3IO_L24P_T3U_N10_64 AF1 64P_L24U1
XCZU3IO_L24P_T3U_N10_66 C9 66P_L24C9
XCZU3IO_L24P_T3U_N10_PERSTN1_I2C_SDA_65 H9 65P_L24C6
XCZU3IO_L2N_AD10N_26 A14 26N_L2B15
XCZU3IO_L2N_AD10N_44 AG11 44N_L2W15
XCZU3IO_L2N_AD14N_24 AH14 24N_L2Y19
XCZU3IO_L2N_AD14N_25 K12 25N_L2F14
XCZU3IO_L2N_T0L_N3_64 AE8 64N_L2V11
XCZU3IO_L2N_T0L_N3_65 V9 65N_L2T5
XCZU3IO_L2N_T0L_N3_66 D1 66N_L2H1
XCZU3IO_L2P_AD10P_26 B14 26P_L2B14
XCZU3IO_L2P_AD10P_44 AF11 44P_L2W14
XCZU3IO_L2P_AD14P_24 AG14 24P_L2Y18
XCZU3IO_L2P_AD14P_25 K13 25P_L2F13
XCZU3IO_L2P_T0L_N2_64 AE9 64P_L2U11
XCZU3IO_L2P_T0L_N2_65 U9 65P_L2R5
XCZU3IO_L2P_T0L_N2_66 E1 66P_L2G1
XCZU3IO_L3N_AD13N_24 AH13 24N_L3Y17
XCZU3IO_L3N_AD13N_25 G10 25N_L3E13
XCZU3IO_L3N_AD9N_26 A13 26N_L3A15
XCZU3IO_L3N_AD9N_44 AH11 44N_L3Y15
XCZU3IO_L3N_T0L_N5_AD15N_64 AC8 64N_L3T9
XCZU3IO_L3N_T0L_N5_AD15N_65 V8 65N_L3P6
XCZU3IO_L3N_T0L_N5_AD15N_66 E2 66N_L3L2
XCZU3IO_L3P_AD13P_24 AG13 24P_L3Y16
XCZU3IO_L3P_AD13P_25 H11 25P_L3E12
XCZU3IO_L3P_AD9P_26 B13 26P_L3A14
XCZU3IO_L3P_AD9P_44 AH12 44P_L3Y14
XCZU3IO_L3P_T0L_N4_AD15P_64 AB8 64P_L3R9
XCZU3IO_L3P_T0L_N4_AD15P_65 U8 65P_L3N6
XCZU3IO_L3P_T0L_N4_AD15P_66 F2 66P_L3K2
XCZU3IO_L4N_AD12N_24 AF13 24N_L4W17
XCZU3IO_L4N_AD12N_25 H12 25N_L4D13
XCZU3IO_L4N_AD8N_26 C13 26N_L4B17
XCZU3IO_L4N_AD8N_44 AF10 44N_L4W13
XCZU3IO_L4N_T0U_N7_DBC_AD7N_64 AE7 64N_L4V8
XCZU3IO_L4N_T0U_N7_DBC_AD7N_65 T8 65N_L4P5
XCZU3IO_L4N_T0U_N7_DBC_AD7N_66 F3 66N_L4J2
XCZU3IO_L4P_AD12P_24 AE13 24P_L4W16
XCZU3IO_L4P_AD12P_25 J12 25P_L4D12
XCZU3IO_L4P_AD8P_26 C14 26P_L4B16
XCZU3IO_L4P_AD8P_44 AE10 44P_L4W12
XCZU3IO_L4P_T0U_N6_DBC_AD7P_64 AD7 64P_L4U8
XCZU3IO_L4P_T0U_N6_DBC_AD7P_66 G3 66P_L4H2
XCZU3IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65 R8 65P_L4N5
XCZU3IO_L5N_HDGC_24 AD14 24N_L5V19
XCZU3IO_L5N_HDGC_25 F10 25N_L5C13
XCZU3IO_L5N_HDGC_AD7N_26 D14 26N_L5C17
XCZU3IO_L5N_HDGC_AD7N_44 AF12 44N_L5V15
XCZU3IO_L5N_T0U_N9_AD14N_64 AC7 64N_L5T8
XCZU3IO_L5N_T0U_N9_AD14N_65 T7 65N_L5M6
XCZU3IO_L5N_T0U_N9_AD14N_66 E3 66N_L5G2
XCZU3IO_L5P_HDGC_24 AD15 24P_L5V18
XCZU3IO_L5P_HDGC_25 G11 25P_L5C12
XCZU3IO_L5P_HDGC_AD7P_26 D15 26P_L5C16
XCZU3IO_L5P_HDGC_AD7P_44 AE12 44P_L5V14
XCZU3IO_L5P_T0U_N8_AD14P_64 AB7 64P_L5R8
XCZU3IO_L5P_T0U_N8_AD14P_65 R7 65P_L5L6
XCZU3IO_L5P_T0U_N8_AD14P_66 E4 66P_L5F2
XCZU3IO_L6N_HDGC_24 AC13 24N_L6V17
XCZU3IO_L6N_HDGC_25 F11 25N_L6D15
XCZU3IO_L6N_HDGC_AD6N_26 E13 26N_L6D17
XCZU3IO_L6N_HDGC_AD6N_44 AD12 44N_L6U15
XCZU3IO_L6N_T0U_N11_AD6N_64 AC6 64N_L6T7
XCZU3IO_L6N_T0U_N11_AD6N_65 T6 65N_L6M5
XCZU3IO_L6N_T0U_N11_AD6N_66 F5 66N_L6H4
XCZU3IO_L6P_HDGC_24 AC14 24P_L6V16
XCZU3IO_L6P_HDGC_25 F12 25P_L6D14
XCZU3IO_L6P_HDGC_AD6P_26 E14 26P_L6D16
XCZU3IO_L6P_HDGC_AD6P_44 AC12 44P_L6U14
XCZU3IO_L6P_T0U_N10_AD6P_64 AB6 64P_L6R7
XCZU3IO_L6P_T0U_N10_AD6P_65 R6 65P_L6L5
XCZU3IO_L6P_T0U_N10_AD6P_66 G5 66P_L6G4
XCZU3IO_L7N_HDGC_24 AB13 24N_L7U17
XCZU3IO_L7N_HDGC_25 D10 25N_L7E15
XCZU3IO_L7N_HDGC_AD5N_26 F13 26N_L7C19
XCZU3IO_L7N_HDGC_AD5N_44 AD10 44N_L7V13
XCZU3IO_L7N_T1L_N1_QBC_AD13N_64 AH9 64N_L7Y11
XCZU3IO_L7N_T1L_N1_QBC_AD13N_65 K1 65N_L7P1
XCZU3IO_L7N_T1L_N1_QBC_AD13N_66 B1 66N_L7F1
XCZU3IO_L7P_HDGC_24 AA13 24P_L7U16
XCZU3IO_L7P_HDGC_25 E10 25P_L7E14
XCZU3IO_L7P_HDGC_AD5P_26 G13 26P_L7C18
XCZU3IO_L7P_HDGC_AD5P_44 AD11 44P_L7V12
XCZU3IO_L7P_T1L_N0_QBC_AD13P_64 AG9 64P_L7W11
XCZU3IO_L7P_T1L_N0_QBC_AD13P_65 L1 65P_L7N1
XCZU3IO_L7P_T1L_N0_QBC_AD13P_66 C1 66P_L7E1
XCZU3IO_L8N_HDGC_24 AB14 24N_L8U19
XCZU3IO_L8N_HDGC_25 D11 25N_L8C15
XCZU3IO_L8N_HDGC_AD4N_26 E15 26N_L8D19
XCZU3IO_L8N_HDGC_AD4N_44 AC11 44N_L8U13
XCZU3IO_L8N_T1L_N3_AD5N_64 AG8 64N_L8Y9
XCZU3IO_L8N_T1L_N3_AD5N_65 H1 65N_L8M1
XCZU3IO_L8N_T1L_N3_AD5N_66 A1 66N_L8D1
XCZU3IO_L8P_HDGC_24 AB15 24P_L8U18
XCZU3IO_L8P_HDGC_25 E12 25P_L8C14
XCZU3IO_L8P_HDGC_AD4P_26 F15 26P_L8D18
XCZU3IO_L8P_HDGC_AD4P_44 AB11 44P_L8U12
XCZU3IO_L8P_T1L_N2_AD5P_64 AF8 64P_L8W9
XCZU3IO_L8P_T1L_N2_AD5P_65 J1 65P_L8L1
XCZU3IO_L8P_T1L_N2_AD5P_66 A2 66P_L8C1
XCZU3IO_L9N_AD11N_24 W13 24N_L9R18
XCZU3IO_L9N_AD11N_25 B10 25N_L9E11
XCZU3IO_L9N_AD3N_26 G14 26N_L9E17
XCZU3IO_L9N_AD3N_44 AA10 44N_L9T12
XCZU3IO_L9N_T1L_N5_AD12N_64 AH7 64N_L9Y10
XCZU3IO_L9N_T1L_N5_AD12N_65 J2 65N_L9N2
XCZU3IO_L9N_T1L_N5_AD12N_66 A3 66N_L9C2
XCZU3IO_L9P_AD11P_24 W14 24P_L9R17
XCZU3IO_L9P_AD11P_25 C11 25P_L9D11
XCZU3IO_L9P_AD3P_26 G15 26P_L9E16
XCZU3IO_L9P_AD3P_44 AA11 44P_L9T11
XCZU3IO_L9P_T1L_N4_AD12P_64 AH8 64P_L9W10
XCZU3IO_L9P_T1L_N4_AD12P_65 K2 65P_L9M2
XCZU3IO_L9P_T1L_N4_AD12P_66 B3 66P_L9B2
XCZU3IO_T0U_N12_VRP_64 AD6 64_T0J5
XCZU3IO_T0U_N12_VRP_65 W9 65_T0P3
XCZU3IO_T0U_N12_VRP_66 G4 66_T0F3
XCZU3IO_T1U_N12_64 AH6 64_T1V3
XCZU3IO_T1U_N12_65 H2 65_T1G3
XCZU3IO_T1U_N12_66 D2 66_T1C3
XCZU3IO_T2U_N12_64 AB5 64_T2R3
XCZU3IO_T2U_N12_65 P9 65_T2B5
XCZU3IO_T2U_N12_66 E7 66_T2D7
XCZU3IO_T3U_N12_64 AE4 64_T3K5
XCZU3IO_T3U_N12_65 K5 65_T3A5
XCZU3IO_T3U_N12_66 C7 66_T3C7
XCZU3NC N1 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC N2 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC N3 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC N4 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC P1 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC P2 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC P4 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC R3 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC R4 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC T1 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC T2 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC T4 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC U3 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC U4 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC U5 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC V1 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC V2 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC V4 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC V5 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC V6 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC W3 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC W4 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC W5 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC Y1 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC Y2 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC Y4 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC Y5 (2)This signal is not brought out to the boundary of the SiP
XCZU3NC Y6 (2)This signal is not brought out to the boundary of the SiP
XCZU3POR_OVERRIDE W7 POR_OVERRIDEJ22Power on reset delay override. Pulled low to GND to set standard PL power on delay time
XCZU3PS_DDR_A0 W28 This signal is connected internally within the SiP
XCZU3PS_DDR_A1 Y28 This signal is connected internally within the SiP
XCZU3PS_DDR_A10 AA25 This signal is connected internally within the SiP
XCZU3PS_DDR_A11 AA26 This signal is connected internally within the SiP
XCZU3PS_DDR_A12 AB25 This signal is connected internally within the SiP
XCZU3PS_DDR_A13 AB26 This signal is connected internally within the SiP
XCZU3PS_DDR_A14 AB24 This signal is connected internally within the SiP
XCZU3PS_DDR_A15 AC24 This signal is connected internally within the SiP
XCZU3PS_DDR_A16 AC23 This signal is connected internally within the SiP
XCZU3PS_DDR_A17 AC22 This signal is connected internally within the SiP
XCZU3PS_DDR_A2 AB28 This signal is connected internally within the SiP
XCZU3PS_DDR_A3 AA28 This signal is connected internally within the SiP
XCZU3PS_DDR_A4 Y27 This signal is connected internally within the SiP
XCZU3PS_DDR_A5 AA27 This signal is connected internally within the SiP
XCZU3PS_DDR_A6 Y22 This signal is connected internally within the SiP
XCZU3PS_DDR_A7 AA23 This signal is connected internally within the SiP
XCZU3PS_DDR_A8 AA22 This signal is connected internally within the SiP
XCZU3PS_DDR_A9 AB23 This signal is connected internally within the SiP
XCZU3PS_DDR_ACT_N Y23 This signal is connected internally within the SiP
XCZU3PS_DDR_ALERT_N U25 This signal is connected internally within the SiP
XCZU3PS_DDR_BA0 V23 This signal is connected internally within the SiP
XCZU3PS_DDR_BA1 W22 This signal is connected internally within the SiP
XCZU3PS_DDR_BG0 W24 This signal is connected internally within the SiP
XCZU3PS_DDR_BG1 V22 This signal is connected internally within the SiP
XCZU3PS_DDR_CK_N0 W26 This signal is connected internally within the SiP
XCZU3PS_DDR_CK_N1 Y25 This signal is connected internally within the SiP
XCZU3PS_DDR_CK0 W25 This signal is connected internally within the SiP
XCZU3PS_DDR_CK1 Y24 This signal is connected internally within the SiP
XCZU3PS_DDR_CKE0 V28 This signal is connected internally within the SiP
XCZU3PS_DDR_CKE1 V27 This signal is connected internally within the SiP
XCZU3PS_DDR_CS_N0 W27 This signal is connected internally within the SiP
XCZU3PS_DDR_CS_N1 V26 This signal is connected internally within the SiP
XCZU3PS_DDR_DM0 AG20 This signal is connected internally within the SiP
XCZU3PS_DDR_DM1 AE23 This signal is connected internally within the SiP
XCZU3PS_DDR_DM2 AE25 This signal is connected internally within the SiP
XCZU3PS_DDR_DM3 AE28 This signal is connected internally within the SiP
XCZU3PS_DDR_DM4 R23 This signal is connected internally within the SiP
XCZU3PS_DDR_DM5 H23 This signal is connected internally within the SiP
XCZU3PS_DDR_DM6 L27 This signal is connected internally within the SiP
XCZU3PS_DDR_DM7 H26 This signal is connected internally within the SiP
XCZU3PS_DDR_DM8 T26 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ0 AD21 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ1 AE20 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ10 AE22 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ11 AD22 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ12 AH23 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ13 AH24 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ14 AE24 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ15 AG24 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ16 AC26 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ17 AD26 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ18 AD25 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ19 AD24 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ2 AD20 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ20 AG26 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ21 AH25 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ22 AH26 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ23 AG25 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ24 AH27 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ25 AH28 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ26 AF28 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ27 AG28 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ28 AC27 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ29 AD27 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ3 AF20 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ30 AD28 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ31 AC28 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ32 T22 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ33 R22 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ34 P22 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ35 N22 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ36 T23 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ37 P24 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ38 R24 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ39 N24 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ4 AH21 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ40 H24 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ41 J24 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ42 M24 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ43 K24 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ44 J22 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ45 H22 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ46 K22 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ47 L22 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ48 M25 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ49 M26 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ5 AH20 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ50 L25 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ51 L26 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ52 K28 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ53 L28 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ54 M28 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ55 N28 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ56 J28 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ57 K27 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ58 H28 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ59 H27 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ6 AH19 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ60 G26 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ61 G25 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ62 K25 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ63 J25 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ64 T28 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ65 R28 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ66 P28 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ67 P27 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ68 P26 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ69 R25 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ7 AG19 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ70 P25 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ71 T25 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ8 AF22 This signal is connected internally within the SiP
XCZU3PS_DDR_DQ9 AH22 This signal is connected internally within the SiP
XCZU3PS_DDR_DQS_N0 AG21 This signal is connected internally within the SiP
XCZU3PS_DDR_DQS_N1 AG23 This signal is connected internally within the SiP
XCZU3PS_DDR_DQS_N2 AF26 This signal is connected internally within the SiP
XCZU3PS_DDR_DQS_N3 AF27 This signal is connected internally within the SiP
XCZU3PS_DDR_DQS_N4 M23 This signal is connected internally within the SiP
XCZU3PS_DDR_DQS_N5 K23 This signal is connected internally within the SiP
XCZU3PS_DDR_DQS_N6 N27 This signal is connected internally within the SiP
XCZU3PS_DDR_DQS_N7 J27 This signal is connected internally within the SiP
XCZU3PS_DDR_DQS_N8 T27 This signal is connected internally within the SiP
XCZU3PS_DDR_DQS_P0 AF21 This signal is connected internally within the SiP
XCZU3PS_DDR_DQS_P1 AF23 This signal is connected internally within the SiP
XCZU3PS_DDR_DQS_P2 AF25 This signal is connected internally within the SiP
XCZU3PS_DDR_DQS_P3 AE27 This signal is connected internally within the SiP
XCZU3PS_DDR_DQS_P4 N23 This signal is connected internally within the SiP
XCZU3PS_DDR_DQS_P5 L23 This signal is connected internally within the SiP
XCZU3PS_DDR_DQS_P6 N26 This signal is connected internally within the SiP
XCZU3PS_DDR_DQS_P7 J26 This signal is connected internally within the SiP
XCZU3PS_DDR_DQS_P8 R27 This signal is connected internally within the SiP
XCZU3PS_DDR_ODT0 U28 This signal is connected internally within the SiP
XCZU3PS_DDR_ODT1 U26 This signal is connected internally within the SiP
XCZU3PS_DDR_PARITY V24 This signal is connected internally within the SiP
XCZU3PS_DDR_RAM_RST_N U23 This signal is connected internally within the SiP
XCZU3PS_DDR_ZQ U24 This signal is connected internally within the SiP
XCZU3PS_DONE M21 PS_DONEN28Indicates the PS configuration is completed
XCZU3PS_ERROR_OUT P17 PS_ERR_OUTL3Asserted for accidental loss of power, a hardware error, or an exception in the PMU
XCZU3PS_ERROR_STATUS M20 PS_ERR_STATM3Indicates a secure lockdown state. Alternatively, it can be used by the PMU firmware to indicate system status
XCZU3PS_INIT_B P21 PS_INIT_BP29Indicates the PL is initialized after a power-on reset (POR). This signal should not be held Low externally to delay the PL configuration sequence because the signal level is not visible to software. However, if there is a CRC error detected when the PL bit stream is loaded PS_INIT_B will be driven low
XCZU3PS_JTAG_TCK R19 PS_TCKT30JTAG
XCZU3PS_JTAG_TDI R18 PS_TDIR29JTAG
XCZU3PS_JTAG_TDO T21 PS_TDOR30JTAG
XCZU3PS_JTAG_TMS N21 PS_TMSR28JTAG
XCZU3PS_MGTRAVCC B22 +MGTRAVCCK26Powered by LDO2. Test point for internal power supply for GTRs
XCZU3PS_MGTRAVCC D22 +MGTRAVCCK26Powered by LDO2. Test point for internal power supply for GTRs
XCZU3PS_MGTRAVTT A23 +MGTRAVTTM26Powered by PMIC1 VO_LDO. Test point for internal power supply for GTRs
XCZU3PS_MGTRAVTT C23 +MGTRAVTTM26Powered by PMIC1 VO_LDO. Test point for internal power supply for GTRs
XCZU3PS_MGTRAVTT D25 +MGTRAVTTM26Powered by PMIC1 VO_LDO. Test point for internal power supply for GTRs
XCZU3PS_MGTRAVTT E23 +MGTRAVTTM26Powered by PMIC1 VO_LDO. Test point for internal power supply for GTRs
XCZU3PS_MGTREFCLK0N_505 F24 GTR_CLK_N0L28GTR Lane 0
XCZU3PS_MGTREFCLK0P_505 F23 GTR_CLK_P0L27GTR Lane 1
XCZU3PS_MGTREFCLK1N_505 E22 GTR_CLK_N1H30GTR Lane 2
XCZU3PS_MGTREFCLK1P_505 E21 GTR_CLK_P1H29GTR Lane 3
XCZU3PS_MGTREFCLK2N_505 C22 GTR_CLK_N2E28GTR Lane 0
XCZU3PS_MGTREFCLK2P_505 C21 GTR_CLK_P2E27GTR Lane 1
XCZU3PS_MGTREFCLK3N_505 A22 GTR_CLK_N3B30GTR Lane 2
XCZU3PS_MGTREFCLK3P_505 A21 GTR_CLK_P3B29GTR Lane 3
XCZU3PS_MGTRREF_505 F22 PS_MGTRREFH26Calibration resistor pin for the termination resistor calibration circuit for the PS-GTR transceivers. Needs to be connected externally. See Schematic Checklist
XCZU3PS_MGTRRXN0_505 F28 GTR_RX_N0K30GTR Lane 0
XCZU3PS_MGTRRXN1_505 D28 GTR_RX_N1J28GTR Lane 1
XCZU3PS_MGTRRXN2_505 B28 GTR_RX_N2D30GTR Lane 2
XCZU3PS_MGTRRXN3_505 A26 GTR_RX_N3C28GTR Lane 3
XCZU3PS_MGTRRXP0_505 F27 GTR_RX_P0K29GTR Lane 0
XCZU3PS_MGTRRXP1_505 D27 GTR_RX_P1J27GTR Lane 1
XCZU3PS_MGTRRXP2_505 B27 GTR_RX_P2D29GTR Lane 2
XCZU3PS_MGTRRXP3_505 A25 GTR_RX_P3C27GTR Lane 3
XCZU3PS_MGTRTXN0_505 E26 GTR_TX_N0M30GTR Lane 0
XCZU3PS_MGTRTXN1_505 D24 GTR_TX_N1G28GTR Lane 1
XCZU3PS_MGTRTXN2_505 C26 GTR_TX_N2F30GTR Lane 2
XCZU3PS_MGTRTXN3_505 B24 GTR_TX_N3A28GTR Lane 3
XCZU3PS_MGTRTXP0_505 E25 GTR_TX_P0M29GTR Lane 0
XCZU3PS_MGTRTXP1_505 D23 GTR_TX_P1G27GTR Lane 1
XCZU3PS_MGTRTXP2_505 C25 GTR_TX_P2F29GTR Lane 2
XCZU3PS_MGTRTXP3_505 B23 GTR_TX_P3A27GTR Lane 3
XCZU3PS_MIO0 AG15 MIO0W20
XCZU3PS_MIO1 AG16 MIO1W21
XCZU3PS_MIO10 AD17 MIO10Y25
XCZU3PS_MIO11 AE17 MIO11V24
XCZU3PS_MIO12 AC17 MIO12W25
XCZU3PS_MIO13 AH18 MIO13Y22
XCZU3PS_MIO14 AG18 MIO14Y23
XCZU3PS_MIO15 AE18 MIO15W24
XCZU3PS_MIO16 AF18 MIO16Y24
XCZU3PS_MIO17 AC18 MIO17W26
XCZU3PS_MIO18 AC19 MIO18V28
XCZU3PS_MIO19 AE19 MIO19Y26
XCZU3PS_MIO2 AF15 MIO2V20
XCZU3PS_MIO20 AD19 MIO20V27
XCZU3PS_MIO21 AC21 MIO21V30
XCZU3PS_MIO22 AB20 MIO22V29
XCZU3PS_MIO23 AB18 MIO23V25
XCZU3PS_MIO24 AB19 MIO24V26
XCZU3PS_MIO25 AB21 MIO25U30
XCZU3PS_MIO26 L15 MIO26U21
XCZU3PS_MIO27 J15 MIO27T20
XCZU3PS_MIO28 K15 MIO28U20
XCZU3PS_MIO29 G16 MIO29T19
XCZU3PS_MIO3 AH15 MIO3Y20
XCZU3PS_MIO30 F16 MIO30R19
XCZU3PS_MIO31 H16 MIO31R20
XCZU3PS_MIO32 J16 MIO32T21
XCZU3PS_MIO33 L16 MIO33U22
XCZU3PS_MIO34 L17 MIO34U23
XCZU3PS_MIO35 H17 MIO35R21
XCZU3PS_MIO36 K17 MIO36T23
XCZU3PS_MIO37 J17 MIO37T22
XCZU3PS_MIO38 H18 MIO38R22
XCZU3PS_MIO39 H19 MIO39R23
XCZU3PS_MIO4 AH16 MIO4Y21
XCZU3PS_MIO40 K18 MIO40T24
XCZU3PS_MIO41 J19 MIO41R24
XCZU3PS_MIO42 L18 MIO42U24
XCZU3PS_MIO43 K19 MIO43U25
XCZU3PS_MIO44 J20 MIO44T25
XCZU3PS_MIO45 K20 MIO45T27
XCZU3PS_MIO46 L20 MIO46T26
XCZU3PS_MIO47 H21 MIO47U26
XCZU3PS_MIO48 J21 MIO48T28
XCZU3PS_MIO49 M18 MIO49U28
XCZU3PS_MIO5 AD16 MIO5W23
XCZU3PS_MIO50 M19 MIO50U29
XCZU3PS_MIO51 L21 MIO51U27
XCZU3PS_MIO52 G18 MIO52P25
XCZU3PS_MIO53 D16 MIO53F20
XCZU3PS_MIO54 F17 MIO54F21
XCZU3PS_MIO55 B16 MIO55E20
XCZU3PS_MIO56 C16 MIO56F19
XCZU3PS_MIO57 A16 MIO57D20
XCZU3PS_MIO58 F18 MIO58L25
XCZU3PS_MIO59 E17 MIO59E21
XCZU3PS_MIO6 AF16 MIO6V21
XCZU3PS_MIO60 C17 MIO60E22
XCZU3PS_MIO61 D17 MIO61F22
XCZU3PS_MIO62 A17 MIO62D23
XCZU3PS_MIO63 E18 MIO63F23
XCZU3PS_MIO64 E19 MIO64F24
XCZU3PS_MIO65 A18 MIO65A24
XCZU3PS_MIO66 G19 MIO66R25
XCZU3PS_MIO67 B18 MIO67B24
XCZU3PS_MIO68 C18 MIO68D24
XCZU3PS_MIO69 D19 MIO69E23
XCZU3PS_MIO7 AH17 MIO7W22
XCZU3PS_MIO70 C19 MIO70C24
XCZU3PS_MIO71 B19 MIO71C25
XCZU3PS_MIO72 G20 MIO72P26
XCZU3PS_MIO73 G21 MIO73R26
XCZU3PS_MIO74 D20 MIO74E24
XCZU3PS_MIO75 A19 MIO75A25
XCZU3PS_MIO76 B20 MIO76E25
XCZU3PS_MIO77 F20 MIO77N25
XCZU3PS_MIO8 AF17 MIO8V22
XCZU3PS_MIO9 AC16 MIO9V23
XCZU3PS_MODE0 P19 PS_MODE0G234-bit boot mode pins sampled on POR de-assertion
XCZU3PS_MODE1 P20 PS_MODE1G244-bit boot mode pins sampled on POR de-assertion
XCZU3PS_MODE2 R20 PS_MODE2J234-bit boot mode pins sampled on POR de-assertion
XCZU3PS_MODE3 T20 PS_MODE3J244-bit boot mode pins sampled on POR de-assertion
XCZU3PS_PADI N17 PS_PADID26Crystal pad input (RTC) 10 Mohm resistor required to be placed between PS_PADI and PS_PADO to use the RTC
XCZU3PS_PADO N18 PS_PADOF26Crystal pad input (RTC) 10 Mohm resistor required to be placed between PS_PADI and PS_PADO to use the RTC
XCZU3PS_POR_B P16 PS_POR_BP30Power-on reset signal (connected internally to PGOOD)
XCZU3PS_PROG_B R17 PS_PROG_BP28PS configuration reset signal
XCZU3PS_REF_CLK R16 PS_REF_CLKB26System reference clock connected to the output of internal 33MHz oscillator
XCZU3PS_SRST_B N19 PS_SRST_BT29System reset commonly used during debug
XCZU3PUDC_B U7 PUDC_BH22Active low input to enable internal pull-ups during configuration on all SelectIO pins. Pin pulled to VCCAUX to disable Weak preconfiguration I/O pull-up resistors
XCZU3RSVDGND U21 VSS(1)
XCZU3RSVDGND V20 VSS(1)
XCZU3RSVDGND V21 VSS(1)
XCZU3RSVDGND W21 VSS(1)
XCZU3RSVDGND Y21 VSS(1)
XCZU3VCC_PSADC Y20 VCC_PSADCY29PS SYSMON ADC supply voltage
XCZU3VCC_PSAUX U19 VCC_PSAUXH24, N23Powered by PMIC2 VOUT_A
XCZU3VCC_PSAUX U20 VCC_PSAUXH24, N23Powered by PMIC2 VOUT_A
XCZU3VCC_PSAUX V19 VCC_PSAUXH24, N23Powered by PMIC2 VOUT_A
XCZU3VCC_PSAUX W19 VCC_PSAUXH24, N23Powered by PMIC2 VOUT_A
XCZU3VCC_PSBATT Y18 VCC_PSBATTA18Battery Input
XCZU3VCC_PSDDR_PLL U16 VCC_PSDDR_PLLB18Need to be Connected externally. See Schematic checklist
XCZU3VCC_PSDDR_PLL U18 VCC_PSDDR_PLLB18Need to be Connected externally. See Schematic checklist
XCZU3VCC_PSINTFP AA15 VCC_PSINTFPJ19, K19Powered by PMIC2 VOUT_D
XCZU3VCC_PSINTFP AA16 VCC_PSINTFPJ19, K19Powered by PMIC2 VOUT_D
XCZU3VCC_PSINTFP AA17 VCC_PSINTFPJ19, K19Powered by PMIC2 VOUT_D
XCZU3VCC_PSINTFP AA18 VCC_PSINTFPJ19, K19Powered by PMIC2 VOUT_D
XCZU3VCC_PSINTFP AB16 VCC_PSINTFPJ19, K19Powered by PMIC2 VOUT_D
XCZU3VCC_PSINTFP Y15 VCC_PSINTFPJ19, K19Powered by PMIC2 VOUT_D
XCZU3VCC_PSINTFP Y17 VCC_PSINTFPJ19, K19Powered by PMIC2 VOUT_D
XCZU3VCC_PSINTFP_DDR AA20 VCC_PSINTFPJ19, K19Powered by PMIC2 VOUT_D
XCZU3VCC_PSINTFP_DDR AA21 VCC_PSINTFPJ19, K19Powered by PMIC2 VOUT_D
XCZU3VCC_PSINTFP_DDR Y19 VCC_PSINTFPJ19, K19Powered by PMIC2 VOUT_D
XCZU3VCC_PSINTLP V16 VCC_PSINTLPL13, M13Powered by PMIC2 VOUT_B
XCZU3VCC_PSINTLP V17 VCC_PSINTLPL13, M13Powered by PMIC2 VOUT_B
XCZU3VCC_PSINTLP V18 VCC_PSINTLPL13, M13Powered by PMIC2 VOUT_B
XCZU3VCC_PSINTLP W15 VCC_PSINTLPL13, M13Powered by PMIC2 VOUT_B
XCZU3VCC_PSINTLP W16 VCC_PSINTLPL13, M13Powered by PMIC2 VOUT_B
XCZU3VCC_PSINTLP W17 VCC_PSINTLPL13, M13Powered by PMIC2 VOUT_B
XCZU3VCC_PSPLL T16 VCC_PSPLLL17Powered by PMIC2 VO_LDO
XCZU3VCC_PSPLL T17 VCC_PSPLLL17Powered by PMIC2 VO_LDO
XCZU3VCC_PSPLL T18 VCC_PSPLLL17Powered by PMIC2 VO_LDO
XCZU3VCCADC P12 VCCADCA20, B20, B21, C20, D21PL System Monitor supply
XCZU3VCCAUX M16 VCCAUXG22, P19Powered by PMIC1 VOUT_A
XCZU3VCCAUX N16 VCCAUXG22, P19Powered by PMIC1 VOUT_A
XCZU3VCCAUX_IO M13 VCCAUXG22, P19Powered by PMIC1 VOUT_A
XCZU3VCCAUX_IO M14 VCCAUXG22, P19Powered by PMIC1 VOUT_A
XCZU3VCCAUX_IO M15 VCCAUXG22, P19Powered by PMIC1 VOUT_A
XCZU3VCCBRAM L11 VCCINTL11, M11Powered by PMIC1 VOUT_D
XCZU3VCCBRAM L12 VCCINTL11, M11Powered by PMIC1 VOUT_D
XCZU3VCCBRAM M11 VCCINTL11, M11Powered by PMIC1 VOUT_D
XCZU3VCCBRAM M12 VCCINTL11, M11Powered by PMIC1 VOUT_D
XCZU3VCCINT N11 VCCINTL11, M11Powered by PMIC1 VOUT_D
XCZU3VCCINT N13 VCCINTL11, M11Powered by PMIC1 VOUT_D
XCZU3VCCINT N15 VCCINTL11, M11Powered by PMIC1 VOUT_D
XCZU3VCCINT P10 VCCINTL11, M11Powered by PMIC1 VOUT_D
XCZU3VCCINT P14 VCCINTL11, M11Powered by PMIC1 VOUT_D
XCZU3VCCINT P15 VCCINTL11, M11Powered by PMIC1 VOUT_D
XCZU3VCCINT R10 VCCINTL11, M11Powered by PMIC1 VOUT_D
XCZU3VCCINT R11 VCCINTL11, M11Powered by PMIC1 VOUT_D
XCZU3VCCINT R14 VCCINTL11, M11Powered by PMIC1 VOUT_D
XCZU3VCCINT T11 VCCINTL11, M11Powered by PMIC1 VOUT_D
XCZU3VCCINT T15 VCCINTL11, M11Powered by PMIC1 VOUT_D
XCZU3VCCINT U10 VCCINTL11, M11Powered by PMIC1 VOUT_D
XCZU3VCCINT U14 VCCINTL11, M11Powered by PMIC1 VOUT_D
XCZU3VCCINT U15 VCCINTL11, M11Powered by PMIC1 VOUT_D
XCZU3VCCINT V10 VCCINTL11, M11Powered by PMIC1 VOUT_D
XCZU3VCCINT V11 VCCINTL11, M11Powered by PMIC1 VOUT_D
XCZU3VCCINT V12 VCCINTL11, M11Powered by PMIC1 VOUT_D
XCZU3VCCINT V14 VCCINTL11, M11Powered by PMIC1 VOUT_D
XCZU3VCCINT_IO K10 VCCINTL11, M11Powered by PMIC1 VOUT_D
XCZU3VCCINT_IO L10 VCCINTL11, M11Powered by PMIC1 VOUT_D
XCZU3VCCINT_IO M10 VCCINTL11, M11Powered by PMIC1 VOUT_D
XCZU3VCCINT_IO M9 VCCINTL11, M11Powered by PMIC1 VOUT_D
XCZU3VCCO_24 AA14 VCCO_HDIO_24P20Need to be Connected externally. See Schematic checklist
XCZU3VCCO_24 AD13 VCCO_HDIO_24P20Need to be Connected externally. See Schematic checklist
XCZU3VCCO_25 B12 VCCO_HDIO_25G20Need to be Connected externally. See Schematic checklist
XCZU3VCCO_25 E11 VCCO_HDIO_25G20Need to be Connected externally. See Schematic checklist
XCZU3VCCO_26 C15 VCCO_HDIO_26G21Need to be Connected externally. See Schematic checklist
XCZU3VCCO_26 F14 VCCO_HDIO_26G21Need to be Connected externally. See Schematic checklist
XCZU3VCCO_44 AC10 VCCO_HDIO_44P18Need to be Connected externally. See Schematic checklist
XCZU3VCCO_44 AG12 VCCO_HDIO_44P18Need to be Connected externally. See Schematic checklist
XCZU3VCCO_64 AC5 VCCO_HPIO_64P14Need to be Connected externally. See Schematic checklist
XCZU3VCCO_64 AD8 VCCO_HPIO_64P14Need to be Connected externally. See Schematic checklist
XCZU3VCCO_64 AG7 VCCO_HPIO_64P14Need to be Connected externally. See Schematic checklist
XCZU3VCCO_65 H5 VCCO_HPIO_65G15Need to be Connected externally. See Schematic checklist
XCZU3VCCO_65 J3 VCCO_HPIO_65G15Need to be Connected externally. See Schematic checklist
XCZU3VCCO_65 L4 VCCO_HPIO_65G15Need to be Connected externally. See Schematic checklist
XCZU3VCCO_66 B7 VCCO_HPIO_66G16Need to be Connected externally. See Schematic checklist
XCZU3VCCO_66 D3 VCCO_HPIO_66G16Need to be Connected externally. See Schematic checklist
XCZU3VCCO_66 E6 VCCO_HPIO_66G16Need to be Connected externally. See Schematic checklist
XCZU3VCCO_PSDDR_504 AB22 VCCO_PSDDRL21Powered by PMIC1 VOUT_C. Only used as a test point
XCZU3VCCO_PSDDR_504 AD23 VCCO_PSDDRL21Powered by PMIC1 VOUT_C. Only used as a test point
XCZU3VCCO_PSDDR_504 AF24 VCCO_PSDDRL21Powered by PMIC1 VOUT_C. Only used as a test point
XCZU3VCCO_PSDDR_504 P23 VCCO_PSDDRL21Powered by PMIC1 VOUT_C. Only used as a test point
XCZU3VCCO_PSDDR_504 T24 VCCO_PSDDRL21Powered by PMIC1 VOUT_C. Only used as a test point
XCZU3VCCO_PSDDR_504 V25 VCCO_PSDDRL21Powered by PMIC1 VOUT_C. Only used as a test point
XCZU3VCCO_PSDDR_504 Y26 VCCO_PSDDRL21Powered by PMIC1 VOUT_C. Only used as a test point
XCZU3VCCO_PSIO0_500 AB17 VCCO_PSIO_500P23Need to be Connected externally. Should be connected to either 1.8V or 3.3V depending on the version of the device. See Schematic checklist.
XCZU3VCCO_PSIO0_500 AE16 VCCO_PSIO_500P23Need to be Connected externally. Should be connected to either 1.8V or 3.3V depending on the version of the device. See Schematic checklist.
XCZU3VCCO_PSIO0_500 AG17 VCCO_PSIO_500P23Need to be Connected externally. Should be connected to either 1.8V or 3.3V depending on the version of the device. See Schematic checklist.
XCZU3VCCO_PSIO1_501 H20 VCCO_PSIO_501J25Need to be Connected externally. See Schematic Checklist
XCZU3VCCO_PSIO1_501 L19 VCCO_PSIO_501J25Need to be Connected externally. See Schematic Checklist
XCZU3VCCO_PSIO2_502 D18 VCCO_PSIO_502G25Need to be Connected externally. See Schematic Checklist
XCZU3VCCO_PSIO2_502 G17 VCCO_PSIO_502G25Need to be Connected externally. See Schematic Checklist
XCZU3VCCO_PSIO3_503 M17 VCCO_PSIO_503H23Need to be Connected externally. See Schematic Checklist
XCZU3VCCO_PSIO3_503 P18 VCCO_PSIO_503H23Need to be Connected externally. See Schematic Checklist
XCZU3VN T12 VNA22System Monitor dedicated differential analog input. Should be tied to GNDADC if unused
XCZU3VP R13 VPA21System Monitor dedicated differential analog input. Should be tied to GNDADC if unused
XCZU3VREF_64 AA7 VREF_64N14Need to be Connected externally. See Schematic Checklist
XCZU3VREF_65 R9 VREF_65H15Need to be Connected externally. See Schematic Checklist
XCZU3VREF_66 G9 VREF_66H16Need to be Connected externally. See Schematic Checklist
XCZU3VREFN R12 VREFNC22Voltage reference GND
XCZU3VREFP T13 VREFPC21Voltage reference input

 

Notes:

(1)See VSS pin in OSD32MP15x datasheet.D4, E10, E11, E12, E13, E14, E15, E4, E5, E6, E7, E8, E9, F10, F11, F12, F13, F14, F15, F4, F5, F6, F7, F8, F9, G11, G12, G13, G14, G15, G5, H13, H14, H15, H5, J13, J14, J15, J16, J5, K13, K14, K15, K16, K5, L13, L14, L15, L5, M11, M12, M13, M14, M15, M5, N10, N11, N12, N13, N14, N15, N5, N6, N7, N8, N9, P5, P6, P7, P8
(2)See RSVD pin in OSDZU3 datasheet.A11, E3, L19, M16, M17, M21, M22, N18, N19, N20, P16, P17, P21, P22, W27, Y27

Revision History

Revision Number Revision Date Changes Author
1 11/27/2023 Initial Version Erik Welsh
Notice
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