Pin Mapping between OSDZU3 and the XCZU3

Published On: December, 15, 2023 By: Erik Welsh

This document is a quick reference to understand the mapping of the pins between the OSDZU3 Family of devices, and the XCZU3 processor. The Pin Map Charts are sortable by both XCZU3 discrete device as well as OSDZU3 system in package.

There are a couple of high level differences between the OSDZU3 and the XCZU3 that are helpful to understand when using this document:
1. The OSDZU3 integrates the DDR. Therefore all DDR related pins are not pinned out on the XCZU3.
2. Mapping sorted by Discrete Device and Signal Names.

An Excel Workbook containing these tables and others can be downloaded here.

These tables have multiple pages. Each column can be sorted using the arrows in the column header. they can be searched by using the respective search box.

OSDZU3 to Discrete Mapping

OSDZU3 Pin Name	OSDZU3 Pin Number	Discrete Device	Discrete Device Signal Name	Discrete Device Pin Number	Comments
DXN	A19	XCZU3	DXN	U12	Temperature sensing diode pin
DXP	B19	XCZU3	DXP	U13	Temperature sensing diode pin
VSS	A1	ALL	GND	(1)
VSS	A26	ALL	GND	(1)
VSS	A29	ALL	GND	(1)
VSS	A30	ALL	GND	(1)
VSS	B1	ALL	GND	(1)
VSS	B25	ALL	GND	(1)
VSS	B27	ALL	GND	(1)
VSS	B28	ALL	GND	(1)
VSS	C26	ALL	GND	(1)
VSS	C29	ALL	GND	(1)
VSS	C30	ALL	GND	(1)
VSS	D25	ALL	GND	(1)
VSS	D27	ALL	GND	(1)
VSS	D28	ALL	GND	(1)
VSS	E26	ALL	GND	(1)
VSS	E29	ALL	GND	(1)
VSS	E30	ALL	GND	(1)
VSS	F27	ALL	GND	(1)
VSS	F28	ALL	GND	(1)
VSS	G10	ALL	GND	(1)
VSS	G11	ALL	GND	(1)
VSS	G12	ALL	GND	(1)
VSS	G13	ALL	GND	(1)
VSS	G17	ALL	GND	(1)
VSS	G18	ALL	GND	(1)
VSS	G19	ALL	GND	(1)
VSS	G26	ALL	GND	(1)
VSS	G29	ALL	GND	(1)
VSS	G30	ALL	GND	(1)
VSS	G7	ALL	GND	(1)
VSS	G8	ALL	GND	(1)
VSS	G9	ALL	GND	(1)
VSS	H10	ALL	GND	(1)
VSS	H11	ALL	GND	(1)
VSS	H12	ALL	GND	(1)
VSS	H13	ALL	GND	(1)
VSS	H14	ALL	GND	(1)
VSS	H17	ALL	GND	(1)
VSS	H18	ALL	GND	(1)
VSS	H19	ALL	GND	(1)
VSS	H20	ALL	GND	(1)
VSS	H21	ALL	GND	(1)
VSS	H25	ALL	GND	(1)
VSS	H27	ALL	GND	(1)
VSS	H28	ALL	GND	(1)
VSS	H7	ALL	GND	(1)
VSS	J11	ALL	GND	(1)
VSS	J12	ALL	GND	(1)
VSS	J13	ALL	GND	(1)
VSS	J14	ALL	GND	(1)
VSS	J15	ALL	GND	(1)
VSS	J16	ALL	GND	(1)
VSS	J17	ALL	GND	(1)
VSS	J18	ALL	GND	(1)
VSS	J20	ALL	GND	(1)
VSS	J21	ALL	GND	(1)
VSS	J26	ALL	GND	(1)
VSS	J29	ALL	GND	(1)
VSS	J30	ALL	GND	(1)
VSS	J7	ALL	GND	(1)
VSS	K11	ALL	GND	(1)
VSS	K12	ALL	GND	(1)
VSS	K13	ALL	GND	(1)
VSS	K14	ALL	GND	(1)
VSS	K15	ALL	GND	(1)
VSS	K16	ALL	GND	(1)
VSS	K17	ALL	GND	(1)
VSS	K18	ALL	GND	(1)
VSS	K20	ALL	GND	(1)
VSS	K21	ALL	GND	(1)
VSS	K22	ALL	GND	(1)
VSS	K23	ALL	GND	(1)
VSS	K24	ALL	GND	(1)
VSS	K25	ALL	GND	(1)
VSS	K27	ALL	GND	(1)
VSS	K28	ALL	GND	(1)
VSS	K7	ALL	GND	(1)
VSS	L12	ALL	GND	(1)
VSS	L14	ALL	GND	(1)
VSS	L15	ALL	GND	(1)
VSS	L16	ALL	GND	(1)
VSS	L18	ALL	GND	(1)
VSS	L20	ALL	GND	(1)
VSS	L22	ALL	GND	(1)
VSS	L23	ALL	GND	(1)
VSS	L24	ALL	GND	(1)
VSS	L26	ALL	GND	(1)
VSS	L29	ALL	GND	(1)
VSS	L30	ALL	GND	(1)
VSS	L7	ALL	GND	(1)
VSS	M12	ALL	GND	(1)
VSS	M14	ALL	GND	(1)
VSS	M15	ALL	GND	(1)
VSS	M18	ALL	GND	(1)
VSS	M19	ALL	GND	(1)
VSS	M20	ALL	GND	(1)
VSS	M23	ALL	GND	(1)
VSS	M24	ALL	GND	(1)
VSS	M25	ALL	GND	(1)
VSS	M27	ALL	GND	(1)
VSS	M28	ALL	GND	(1)
VSS	M7	ALL	GND	(1)
VSS	N11	ALL	GND	(1)
VSS	N12	ALL	GND	(1)
VSS	N13	ALL	GND	(1)
VSS	N15	ALL	GND	(1)
VSS	N16	ALL	GND	(1)
VSS	N17	ALL	GND	(1)
VSS	N21	ALL	GND	(1)
VSS	N22	ALL	GND	(1)
VSS	N26	ALL	GND	(1)
VSS	N29	ALL	GND	(1)
VSS	N30	ALL	GND	(1)
VSS	N7	ALL	GND	(1)
VSS	P10	ALL	GND	(1)
VSS	P11	ALL	GND	(1)
VSS	P12	ALL	GND	(1)
VSS	P13	ALL	GND	(1)
VSS	P7	ALL	GND	(1)
VSS	P8	ALL	GND	(1)
VSS	P9	ALL	GND	(1)
VSS	W1	ALL	GND	(1)
VSS	W28	ALL	GND	(1)
VSS	W29	ALL	GND	(1)
VSS	W30	ALL	GND	(1)
VSS	Y1	ALL	GND	(1)
VSS	Y28	ALL	GND	(1)
GND_PSADC	Y30	XCZU3	GND_PSADC	W20
GNDADC	A23	XCZU3	GNDADC	P13
GNDADC	B22	XCZU3	GNDADC	P13
GNDADC	B23	XCZU3	GNDADC	P13
GNDADC	C23	XCZU3	GNDADC	P13
GNDADC	D22	XCZU3	GNDADC	P13
24N_L10	T18	XCZU3	IO_L10N_AD10N_24	Y13
25N_L10	C11	XCZU3	IO_L10N_AD10N_25	A10
26N_L10	F16	XCZU3	IO_L10N_AD2N_26	H13
44N_L10	R12	XCZU3	IO_L10N_AD2N_44	Y10
64N_L10	Y8	XCZU3	IO_L10N_T1U_N7_QBC_AD4N_64	AG5
65N_L10	K4	XCZU3	IO_L10N_T1U_N7_QBC_AD4N_65	H3
66N_L10	B3	XCZU3	IO_L10N_T1U_N7_QBC_AD4N_66	A4
24P_L10	T17	XCZU3	IO_L10P_AD10P_24	Y14
25P_L10	B11	XCZU3	IO_L10P_AD10P_25	B11
26P_L10	F15	XCZU3	IO_L10P_AD2P_26	H14
44P_L10	R11	XCZU3	IO_L10P_AD2P_44	W10
64P_L10	W8	XCZU3	IO_L10P_T1U_N6_QBC_AD4P_64	AG6
65P_L10	J4	XCZU3	IO_L10P_T1U_N6_QBC_AD4P_65	H4
66P_L10	A3	XCZU3	IO_L10P_T1U_N6_QBC_AD4P_66	B4
26N_L11	E19	XCZU3	IO_L11N_AD1N_26	J14
44N_L11	R14	XCZU3	IO_L11N_AD1N_44	AA8
24N_L11	R16	XCZU3	IO_L11N_AD9N_24	W11
25N_L11	A13	XCZU3	IO_L11N_AD9N_25	A11
64N_L11	T10	XCZU3	IO_L11N_T1U_N9_GC_64	AF6
65N_L11	M4	XCZU3	IO_L11N_T1U_N9_GC_65	K3
66N_L11	D4	XCZU3	IO_L11N_T1U_N9_GC_66	C4
26P_L11	E18	XCZU3	IO_L11P_AD1P_26	K14
44P_L11	R13	XCZU3	IO_L11P_AD1P_44	Y9
24P_L11	R15	XCZU3	IO_L11P_AD9P_24	W12
25P_L11	A12	XCZU3	IO_L11P_AD9P_25	A12
64P_L11	R10	XCZU3	IO_L11P_T1U_N8_GC_64	AF7
65P_L11	L4	XCZU3	IO_L11P_T1U_N8_GC_65	K4
66P_L11	C4	XCZU3	IO_L11P_T1U_N8_GC_66	D4
26N_L12	F18	XCZU3	IO_L12N_AD0N_26	L13
44N_L12	T14	XCZU3	IO_L12N_AD0N_44	AB9
24N_L12	T16	XCZU3	IO_L12N_AD8N_24	AA12
25N_L12	B13	XCZU3	IO_L12N_AD8N_25	C12
64N_L12	V10	XCZU3	IO_L12N_T1U_N11_GC_64	AF5
65N_L12	R2	XCZU3	IO_L12N_T1U_N11_GC_65	L2
66N_L12	E2	XCZU3	IO_L12N_T1U_N11_GC_66	C2
26P_L12	F17	XCZU3	IO_L12P_AD0P_26	L14
44P_L12	T13	XCZU3	IO_L12P_AD0P_44	AB10
24P_L12	T15	XCZU3	IO_L12P_AD8P_24	Y12
25P_L12	B12	XCZU3	IO_L12P_AD8P_25	D12
64P_L12	U10	XCZU3	IO_L12P_T1U_N10_GC_64	AE5
65P_L12	P2	XCZU3	IO_L12P_T1U_N10_GC_65	L3
66P_L12	D2	XCZU3	IO_L12P_T1U_N10_GC_66	C3
64N_L13	V7	XCZU3	IO_L13N_T2L_N1_GC_QBC_64	AD4
65N_L13	H5	XCZU3	IO_L13N_T2L_N1_GC_QBC_65	L6
66N_L13	B8	XCZU3	IO_L13N_T2L_N1_GC_QBC_66	D6
64P_L13	U7	XCZU3	IO_L13P_T2L_N0_GC_QBC_64	AD5
65P_L13	G5	XCZU3	IO_L13P_T2L_N0_GC_QBC_65	L7
66P_L13	A8	XCZU3	IO_L13P_T2L_N0_GC_QBC_66	D7
64N_L14	V5	XCZU3	IO_L14N_T2L_N3_GC_64	AC3
65N_L14	F5	XCZU3	IO_L14N_T2L_N3_GC_65	L5
66N_L14	F4	XCZU3	IO_L14N_T2L_N3_GC_66	D5
64P_L14	U5	XCZU3	IO_L14P_T2L_N2_GC_64	AC4
65P_L14	E5	XCZU3	IO_L14P_T2L_N2_GC_65	M6
66P_L14	E4	XCZU3	IO_L14P_T2L_N2_GC_66	E5
64N_L15	V6	XCZU3	IO_L15N_T2L_N5_AD11N_64	AB3
65N_L15	T4	XCZU3	IO_L15N_T2L_N5_AD11N_65	N6
66N_L15	D8	XCZU3	IO_L15N_T2L_N5_AD11N_66	F6
64P_L15	U6	XCZU3	IO_L15P_T2L_N4_AD11P_64	AB4
65P_L15	R4	XCZU3	IO_L15P_T2L_N4_AD11P_65	N7
66P_L15	C8	XCZU3	IO_L15P_T2L_N4_AD11P_66	G6
64N_L16	W2	XCZU3	IO_L16N_T2U_N7_QBC_AD3N_64	AD1
65N_L16	V4	XCZU3	IO_L16N_T2U_N7_QBC_AD3N_65	P6
66N_L16	F10	XCZU3	IO_L16N_T2U_N7_QBC_AD3N_66	F7
64P_L16	V2	XCZU3	IO_L16P_T2U_N6_QBC_AD3P_64	AD2
65P_L16	U4	XCZU3	IO_L16P_T2U_N6_QBC_AD3P_65	P7
66P_L16	E10	XCZU3	IO_L16P_T2U_N6_QBC_AD3P_66	G8
64N_L17	U2	XCZU3	IO_L17N_T2U_N9_AD10N_64	AC2
65N_L17	K6	XCZU3	IO_L17N_T2U_N9_AD10N_65	N8
66N_L17	D10	XCZU3	IO_L17N_T2U_N9_AD10N_66	E8
64P_L17	T2	XCZU3	IO_L17P_T2U_N8_AD10P_64	AB2
65P_L17	J6	XCZU3	IO_L17P_T2U_N8_AD10P_65	N9
66P_L17	C10	XCZU3	IO_L17P_T2U_N8_AD10P_66	F8
64N_L18	T1	XCZU3	IO_L18N_T2U_N11_AD2N_64	AC1
65N_L18	H6	XCZU3	IO_L18N_T2U_N11_AD2N_65	L8
66N_L18	B10	XCZU3	IO_L18N_T2U_N11_AD2N_66	D9
64P_L18	R1	XCZU3	IO_L18P_T2U_N10_AD2P_64	AB1
65P_L18	G6	XCZU3	IO_L18P_T2U_N10_AD2P_65	M8
66P_L18	A10	XCZU3	IO_L18P_T2U_N10_AD2P_66	E9
64N_L19	Y7	XCZU3	IO_L19N_T3L_N1_DBC_AD9N_64	AH4
65N_L19	B6	XCZU3	IO_L19N_T3L_N1_DBC_AD9N_65	J4
66N_L19	B4	XCZU3	IO_L19N_T3L_N1_DBC_AD9N_66	A5
64P_L19	W7	XCZU3	IO_L19P_T3L_N0_DBC_AD9P_64	AG4
65P_L19	A6	XCZU3	IO_L19P_T3L_N0_DBC_AD9P_65	J5
66P_L19	A4	XCZU3	IO_L19P_T3L_N0_DBC_AD9P_66	B5
26N_L1	A17	XCZU3	IO_L1N_AD11N_26	A15
44N_L1	Y13	XCZU3	IO_L1N_AD11N_44	AH10
24N_L1	W19	XCZU3	IO_L1N_AD15N_24	AE14
25N_L1	F12	XCZU3	IO_L1N_AD15N_25	J10
64N_L1	V9	XCZU3	IO_L1N_T0L_N1_DBC_64	AD9
65N_L1	T6	XCZU3	IO_L1N_T0L_N1_DBC_65	Y8
66N_L1	K1	XCZU3	IO_L1N_T0L_N1_DBC_66	F1
26P_L1	A16	XCZU3	IO_L1P_AD11P_26	B15
44P_L1	Y12	XCZU3	IO_L1P_AD11P_44	AG10
24P_L1	W18	XCZU3	IO_L1P_AD15P_24	AE15
25P_L1	F11	XCZU3	IO_L1P_AD15P_25	J11
64P_L1	U9	XCZU3	IO_L1P_T0L_N0_DBC_64	AC9
65P_L1	R6	XCZU3	IO_L1P_T0L_N0_DBC_65	W8
66P_L1	J1	XCZU3	IO_L1P_T0L_N0_DBC_66	G1
64N_L20	Y6	XCZU3	IO_L20N_T3L_N3_AD1N_64	AH3
65N_L20	F8	XCZU3	IO_L20N_T3L_N3_AD1N_65	H6
66N_L20	F7	XCZU3	IO_L20N_T3L_N3_AD1N_66	B6
64P_L20	W6	XCZU3	IO_L20P_T3L_N2_AD1P_64	AG3
65P_L20	E8	XCZU3	IO_L20P_T3L_N2_AD1P_65	J6
66P_L20	E7	XCZU3	IO_L20P_T3L_N2_AD1P_66	C6
64N_L21	Y5	XCZU3	IO_L21N_T3L_N5_AD8N_64	AF3
65N_L21	D5	XCZU3	IO_L21N_T3L_N5_AD8N_65	H7
66N_L21	B7	XCZU3	IO_L21N_T3L_N5_AD8N_66	A6
64P_L21	W5	XCZU3	IO_L21P_T3L_N4_AD8P_64	AE3
65P_L21	C5	XCZU3	IO_L21P_T3L_N4_AD8P_65	J7
66P_L21	A7	XCZU3	IO_L21P_T3L_N4_AD8P_66	A7
64N_L22	Y4	XCZU3	IO_L22N_T3U_N7_DBC_AD0N_64	AF2
65N_L22	P4	XCZU3	IO_L22N_T3U_N7_DBC_AD0N_65	K7
66N_L22	F9	XCZU3	IO_L22N_T3U_N7_DBC_AD0N_66	B8
64P_L22	W4	XCZU3	IO_L22P_T3U_N6_DBC_AD0P_64	AE2
65P_L22	N4	XCZU3	IO_L22P_T3U_N6_DBC_AD0P_65	K8
66P_L22	E9	XCZU3	IO_L22P_T3U_N6_DBC_AD0P_66	C8
64N_L23	Y3	XCZU3	IO_L23N_T3U_N9_64	AH1
65N_L23	F6	XCZU3	IO_L23N_T3U_N9_65	J9
66N_L23	B9	XCZU3	IO_L23N_T3U_N9_66	A8
64P_L23	W3	XCZU3	IO_L23P_T3U_N8_64	AH2
66P_L23	A9	XCZU3	IO_L23P_T3U_N8_66	A9
65P_L23	E6	XCZU3	IO_L23P_T3U_N8_I2C_SCLK_65	K9
64N_L24	V1	XCZU3	IO_L24N_T3U_N11_64	AG1
66N_L24	D9	XCZU3	IO_L24N_T3U_N11_66	B9
65N_L24	D6	XCZU3	IO_L24N_T3U_N11_PERSTN0_65	H8
64P_L24	U1	XCZU3	IO_L24P_T3U_N10_64	AF1
66P_L24	C9	XCZU3	IO_L24P_T3U_N10_66	C9
65P_L24	C6	XCZU3	IO_L24P_T3U_N10_PERSTN1_I2C_SDA_65	H9
26N_L2	B15	XCZU3	IO_L2N_AD10N_26	A14
44N_L2	W15	XCZU3	IO_L2N_AD10N_44	AG11
24N_L2	Y19	XCZU3	IO_L2N_AD14N_24	AH14
25N_L2	F14	XCZU3	IO_L2N_AD14N_25	K12
64N_L2	V11	XCZU3	IO_L2N_T0L_N3_64	AE8
65N_L2	T5	XCZU3	IO_L2N_T0L_N3_65	V9
66N_L2	H1	XCZU3	IO_L2N_T0L_N3_66	D1
26P_L2	B14	XCZU3	IO_L2P_AD10P_26	B14
44P_L2	W14	XCZU3	IO_L2P_AD10P_44	AF11
24P_L2	Y18	XCZU3	IO_L2P_AD14P_24	AG14
25P_L2	F13	XCZU3	IO_L2P_AD14P_25	K13
64P_L2	U11	XCZU3	IO_L2P_T0L_N2_64	AE9
65P_L2	R5	XCZU3	IO_L2P_T0L_N2_65	U9
66P_L2	G1	XCZU3	IO_L2P_T0L_N2_66	E1
24N_L3	Y17	XCZU3	IO_L3N_AD13N_24	AH13
25N_L3	E13	XCZU3	IO_L3N_AD13N_25	G10
26N_L3	A15	XCZU3	IO_L3N_AD9N_26	A13
44N_L3	Y15	XCZU3	IO_L3N_AD9N_44	AH11
64N_L3	T9	XCZU3	IO_L3N_T0L_N5_AD15N_64	AC8
65N_L3	P6	XCZU3	IO_L3N_T0L_N5_AD15N_65	V8
66N_L3	L2	XCZU3	IO_L3N_T0L_N5_AD15N_66	E2
24P_L3	Y16	XCZU3	IO_L3P_AD13P_24	AG13
25P_L3	E12	XCZU3	IO_L3P_AD13P_25	H11
26P_L3	A14	XCZU3	IO_L3P_AD9P_26	B13
44P_L3	Y14	XCZU3	IO_L3P_AD9P_44	AH12
64P_L3	R9	XCZU3	IO_L3P_T0L_N4_AD15P_64	AB8
65P_L3	N6	XCZU3	IO_L3P_T0L_N4_AD15P_65	U8
66P_L3	K2	XCZU3	IO_L3P_T0L_N4_AD15P_66	F2
24N_L4	W17	XCZU3	IO_L4N_AD12N_24	AF13
25N_L4	D13	XCZU3	IO_L4N_AD12N_25	H12
26N_L4	B17	XCZU3	IO_L4N_AD8N_26	C13
44N_L4	W13	XCZU3	IO_L4N_AD8N_44	AF10
64N_L4	V8	XCZU3	IO_L4N_T0U_N7_DBC_AD7N_64	AE7
65N_L4	P5	XCZU3	IO_L4N_T0U_N7_DBC_AD7N_65	T8
66N_L4	J2	XCZU3	IO_L4N_T0U_N7_DBC_AD7N_66	F3
24P_L4	W16	XCZU3	IO_L4P_AD12P_24	AE13
25P_L4	D12	XCZU3	IO_L4P_AD12P_25	J12
26P_L4	B16	XCZU3	IO_L4P_AD8P_26	C14
44P_L4	W12	XCZU3	IO_L4P_AD8P_44	AE10
64P_L4	U8	XCZU3	IO_L4P_T0U_N6_DBC_AD7P_64	AD7
66P_L4	H2	XCZU3	IO_L4P_T0U_N6_DBC_AD7P_66	G3
65P_L4	N5	XCZU3	IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65	R8
24N_L5	V19	XCZU3	IO_L5N_HDGC_24	AD14
25N_L5	C13	XCZU3	IO_L5N_HDGC_25	F10
26N_L5	C17	XCZU3	IO_L5N_HDGC_AD7N_26	D14
44N_L5	V15	XCZU3	IO_L5N_HDGC_AD7N_44	AF12
64N_L5	T8	XCZU3	IO_L5N_T0U_N9_AD14N_64	AC7
65N_L5	M6	XCZU3	IO_L5N_T0U_N9_AD14N_65	T7
66N_L5	G2	XCZU3	IO_L5N_T0U_N9_AD14N_66	E3
24P_L5	V18	XCZU3	IO_L5P_HDGC_24	AD15
25P_L5	C12	XCZU3	IO_L5P_HDGC_25	G11
26P_L5	C16	XCZU3	IO_L5P_HDGC_AD7P_26	D15
44P_L5	V14	XCZU3	IO_L5P_HDGC_AD7P_44	AE12
64P_L5	R8	XCZU3	IO_L5P_T0U_N8_AD14P_64	AB7
65P_L5	L6	XCZU3	IO_L5P_T0U_N8_AD14P_65	R7
66P_L5	F2	XCZU3	IO_L5P_T0U_N8_AD14P_66	E4
24N_L6	V17	XCZU3	IO_L6N_HDGC_24	AC13
25N_L6	D15	XCZU3	IO_L6N_HDGC_25	F11
26N_L6	D17	XCZU3	IO_L6N_HDGC_AD6N_26	E13
44N_L6	U15	XCZU3	IO_L6N_HDGC_AD6N_44	AD12
64N_L6	T7	XCZU3	IO_L6N_T0U_N11_AD6N_64	AC6
65N_L6	M5	XCZU3	IO_L6N_T0U_N11_AD6N_65	T6
66N_L6	H4	XCZU3	IO_L6N_T0U_N11_AD6N_66	F5
24P_L6	V16	XCZU3	IO_L6P_HDGC_24	AC14
25P_L6	D14	XCZU3	IO_L6P_HDGC_25	F12
26P_L6	D16	XCZU3	IO_L6P_HDGC_AD6P_26	E14
44P_L6	U14	XCZU3	IO_L6P_HDGC_AD6P_44	AC12
64P_L6	R7	XCZU3	IO_L6P_T0U_N10_AD6P_64	AB6
65P_L6	L5	XCZU3	IO_L6P_T0U_N10_AD6P_65	R6
66P_L6	G4	XCZU3	IO_L6P_T0U_N10_AD6P_66	G5
24N_L7	U17	XCZU3	IO_L7N_HDGC_24	AB13
25N_L7	E15	XCZU3	IO_L7N_HDGC_25	D10
26N_L7	C19	XCZU3	IO_L7N_HDGC_AD5N_26	F13
44N_L7	V13	XCZU3	IO_L7N_HDGC_AD5N_44	AD10
64N_L7	Y11	XCZU3	IO_L7N_T1L_N1_QBC_AD13N_64	AH9
65N_L7	P1	XCZU3	IO_L7N_T1L_N1_QBC_AD13N_65	K1
66N_L7	F1	XCZU3	IO_L7N_T1L_N1_QBC_AD13N_66	B1
24P_L7	U16	XCZU3	IO_L7P_HDGC_24	AA13
25P_L7	E14	XCZU3	IO_L7P_HDGC_25	E10
26P_L7	C18	XCZU3	IO_L7P_HDGC_AD5P_26	G13
44P_L7	V12	XCZU3	IO_L7P_HDGC_AD5P_44	AD11
64P_L7	W11	XCZU3	IO_L7P_T1L_N0_QBC_AD13P_64	AG9
65P_L7	N1	XCZU3	IO_L7P_T1L_N0_QBC_AD13P_65	L1
66P_L7	E1	XCZU3	IO_L7P_T1L_N0_QBC_AD13P_66	C1
24N_L8	U19	XCZU3	IO_L8N_HDGC_24	AB14
25N_L8	C15	XCZU3	IO_L8N_HDGC_25	D11
26N_L8	D19	XCZU3	IO_L8N_HDGC_AD4N_26	E15
44N_L8	U13	XCZU3	IO_L8N_HDGC_AD4N_44	AC11
64N_L8	Y9	XCZU3	IO_L8N_T1L_N3_AD5N_64	AG8
65N_L8	M1	XCZU3	IO_L8N_T1L_N3_AD5N_65	H1
66N_L8	D1	XCZU3	IO_L8N_T1L_N3_AD5N_66	A1
24P_L8	U18	XCZU3	IO_L8P_HDGC_24	AB15
25P_L8	C14	XCZU3	IO_L8P_HDGC_25	E12
26P_L8	D18	XCZU3	IO_L8P_HDGC_AD4P_26	F15
44P_L8	U12	XCZU3	IO_L8P_HDGC_AD4P_44	AB11
64P_L8	W9	XCZU3	IO_L8P_T1L_N2_AD5P_64	AF8
65P_L8	L1	XCZU3	IO_L8P_T1L_N2_AD5P_65	J1
66P_L8	C1	XCZU3	IO_L8P_T1L_N2_AD5P_66	A2
24N_L9	R18	XCZU3	IO_L9N_AD11N_24	W13
25N_L9	E11	XCZU3	IO_L9N_AD11N_25	B10
26N_L9	E17	XCZU3	IO_L9N_AD3N_26	G14
44N_L9	T12	XCZU3	IO_L9N_AD3N_44	AA10
64N_L9	Y10	XCZU3	IO_L9N_T1L_N5_AD12N_64	AH7
65N_L9	N2	XCZU3	IO_L9N_T1L_N5_AD12N_65	J2
66N_L9	C2	XCZU3	IO_L9N_T1L_N5_AD12N_66	A3
24P_L9	R17	XCZU3	IO_L9P_AD11P_24	W14
25P_L9	D11	XCZU3	IO_L9P_AD11P_25	C11
26P_L9	E16	XCZU3	IO_L9P_AD3P_26	G15
44P_L9	T11	XCZU3	IO_L9P_AD3P_44	AA11
64P_L9	W10	XCZU3	IO_L9P_T1L_N4_AD12P_64	AH8
65P_L9	M2	XCZU3	IO_L9P_T1L_N4_AD12P_65	K2
66P_L9	B2	XCZU3	IO_L9P_T1L_N4_AD12P_66	B3
64_T0	J5	XCZU3	IO_T0U_N12_VRP_64	AD6
65_T0	P3	XCZU3	IO_T0U_N12_VRP_65	W9
66_T0	F3	XCZU3	IO_T0U_N12_VRP_66	G4
64_T1	V3	XCZU3	IO_T1U_N12_64	AH6
65_T1	G3	XCZU3	IO_T1U_N12_65	H2
66_T1	C3	XCZU3	IO_T1U_N12_66	D2
64_T2	R3	XCZU3	IO_T2U_N12_64	AB5
65_T2	B5	XCZU3	IO_T2U_N12_65	P9
66_T2	D7	XCZU3	IO_T2U_N12_66	E7
64_T3	K5	XCZU3	IO_T3U_N12_64	AE4
65_T3	A5	XCZU3	IO_T3U_N12_65	K5
66_T3	C7	XCZU3	IO_T3U_N12_66	C7
+3V3_ON	N24	PMIC	Not connected to the ZU3	N/A	Powered by LDO1. Powers EEPROM.
+3V3_ON	P24	PMIC	Not connected to the ZU3	N/A	Powered by LDO1. Powers EEPROM.
+5V_IN	H8	PMIC	Not Connected to the ZU3	N/A	Power Input to OSDZU3 Device
+5V_IN	H9	PMIC	Not Connected to the ZU3	N/A	Power Input to OSDZU3 Device
+5V_IN	J8	PMIC	Not Connected to the ZU3	N/A	Power Input to OSDZU3 Device
+5V_IN	J9	PMIC	Not Connected to the ZU3	N/A	Power Input to OSDZU3 Device
+5V_IN	K8	PMIC	Not Connected to the ZU3	N/A	Power Input to OSDZU3 Device
+5V_IN	K9	PMIC	Not Connected to the ZU3	N/A	Power Input to OSDZU3 Device
+5V_IN	L8	PMIC	Not Connected to the ZU3	N/A	Power Input to OSDZU3 Device
+5V_IN	L9	PMIC	Not Connected to the ZU3	N/A	Power Input to OSDZU3 Device
+5V_IN	M8	PMIC	Not Connected to the ZU3	N/A	Power Input to OSDZU3 Device
+5V_IN	M9	PMIC	Not Connected to the ZU3	N/A	Power Input to OSDZU3 Device
+5V_IN	N8	PMIC	Not Connected to the ZU3	N/A	Power Input to OSDZU3 Device
+5V_IN	N9	PMIC	Not Connected to the ZU3	N/A	Power Input to OSDZU3 Device
PMIC2_C	J10	PMIC	Not connected to the ZU3	N/A	Powered by PMIC2 VOUT_C
PMIC2_C	K10	PMIC	Not connected to the ZU3	N/A	Powered by PMIC2 VOUT_C
PMIC2_C	L10	PMIC	Not connected to the ZU3	N/A	Powered by PMIC2 VOUT_C
PMIC2_C	M10	PMIC	Not connected to the ZU3	N/A	Powered by PMIC2 VOUT_C
VSUPPLY	N10	PMIC	Not Connected to the ZU3	N/A	Power Input to OSDZU3 Device
EEPROM_WP	N27	EEPROM	Not connected to ZU3	N/A	EEPROM write protect. Internally pulled up to +3V3_ON to enable Write Protect to EEPROM by default. Connect to GND to disable write protect.
GND_ANA	A2	PMIC	Not connected to ZU3	N/A	PMIC analog GND
GND_ANA	Y2	PMIC	Not connected to ZU3	N/A	PMIC analog GND
OSC_OE	F25	OSCILLATOR	Not connected to ZU3	N/A	33MHz Oscillator enable. Internally pulled up to VCC_PSAUX to enable 33MHz oscillator
PGOOD	J3	PMIC	Not connected to ZU3	N/A	PMIC1 and PMIC2 Power Good output indicating proper operation of all power rails
PMIC_IRQB	K3	PMIC	Not connected to ZU3	N/A	PMIC1/2 Alert# line. Pulled up to VDDIO through 10K resistor.
PMIC_SCL	P27	PMIC	Not connected to ZU3	N/A	Connected to I2C of PMIC1/2 and EEPROM
PMIC_SDA	R27	PMIC	Not connected to ZU3	N/A	Connected to I2C of PMIC1/2 and EEPROM
PMIC_SLEEP	T3	PMIC	Not connected to ZU3	N/A	PMIC1/2 sleep mode control, +3V3_ON LDO enable pin, internally pulled up to +5V_IN
PMIC1_B	G14	PMIC	Not connected to ZU3	N/A	External use. Powered by PMIC1 VOUT_B
PMIC1_B	P15	PMIC	Not connected to ZU3	N/A	External use. Powered by PMIC1 VOUT_B
PMIC1_MTP	U3	PMIC	Not connected to ZU3	N/A	Tie to GND through a 2.32Kohm Resistor for default operation
PMIC2_MTP	D3	PMIC	Not connected to ZU3	N/A	Tie to GND through a 2.87Kohm Resistor for default operation
PWR_EN	H3	PMIC	Not connected to Zu3	N/A	PMIC1/2 power rails enable pin. Internally pulled up to +3V3_ON
RSVD	A11	N/A	Not connected to ZU3	N/A	Reserved for future use. Do not connect (2)
RSVD	E3	N/A	Not connected to ZU3	N/A	Reserved for future use. Do not connect (2)
RSVD	L19	N/A	Not connected to ZU3	N/A	Reserved for future use. Do not connect (2)
RSVD	M16	N/A	Not connected to ZU3	N/A	Reserved for future use. Do not connect (2)
RSVD	M17	N/A	Not connected to ZU3	N/A	Reserved for future use. Do not connect (2)
RSVD	M21	N/A	Not connected to ZU3	N/A	Reserved for future use. Do not connect (2)
RSVD	M22	N/A	Not connected to ZU3	N/A	Reserved for future use. Do not connect (2)
RSVD	N18	N/A	Not connected to ZU3	N/A	Reserved for future use. Do not connect (2)
RSVD	N19	N/A	Not connected to ZU3	N/A	Reserved for future use. Do not connect (2)
RSVD	N20	N/A	Not connected to ZU3	N/A	Reserved for future use. Do not connect (2)
RSVD	P16	N/A	Not connected to ZU3	N/A	Reserved for future use. Do not connect (2)
RSVD	P17	N/A	Not connected to ZU3	N/A	Reserved for future use. Do not connect (2)
RSVD	P21	N/A	Not connected to ZU3	N/A	Reserved for future use. Do not connect (2)
RSVD	P22	N/A	Not connected to ZU3	N/A	Reserved for future use. Do not connect (2)
RSVD	W27	N/A	Not connected to ZU3	N/A	Reserved for future use. Do not connect (2)
RSVD	Y27	N/A	Not connected to ZU3	N/A	Reserved for future use. Do not connect (2)
VDDIO	N3	XCZU3	Not connected to ZU3	N/A	PMIC1/2 IO control voltage, MUST be connected to a 3.3V power source to set 3.3V I2C interface
POR_OVERRIDE	J22	XCZU3	POR_OVERRIDE	W7	Power on reset delay override. Pulled low to GND to set standard PL power on delay time
PS_DONE	N28	XCZU3	PS_DONE	M21	Indicates the PS configuration is completed
PS_ERR_OUT	L3	XCZU3	PS_ERROR_OUT	P17	Asserted for accidental loss of power, a hardware error, or an exception in the PMU
PS_ERR_STAT	M3	XCZU3	PS_ERROR_STATUS	M20	Indicates a secure lockdown state. Alternatively, it can be used by the PMU firmware to indicate system status
PS_INIT_B	P29	XCZU3	PS_INIT_B	P21	Indicates the PL is initialized after a power-on reset (POR). This signal should not be held Low externally to delay the PL configuration sequence because the signal level is not visible to software. However, if there is a CRC error detected when the PL bit stream is loaded PS_INIT_B will be driven low
PS_TCK	T30	XCZU3	PS_JTAG_TCK	R19	JTAG
PS_TDI	R29	XCZU3	PS_JTAG_TDI	R18	JTAG
PS_TDO	R30	XCZU3	PS_JTAG_TDO	T21	JTAG
PS_TMS	R28	XCZU3	PS_JTAG_TMS	N21	JTAG
+MGTRAVCC	K26	XCZU3	PS_MGTRAVCC	B22, D22	Powered by LDO2. Test point for internal power supply for GTRs
+MGTRAVTT	M26	XCZU3	PS_MGTRAVTT	A23, C23, D25, E23	Powered by PMIC1 VO_LDO. Test point for internal power supply for GTRs
GTR_CLK_N0	L28	XCZU3	PS_MGTREFCLK0N_505	F24	GTR Lane 0
GTR_CLK_P0	L27	XCZU3	PS_MGTREFCLK0P_505	F23	GTR Lane 0
GTR_CLK_N1	H30	XCZU3	PS_MGTREFCLK1N_505	E22	GTR Lane 1
GTR_CLK_P1	H29	XCZU3	PS_MGTREFCLK1P_505	E21	GTR Lane 1
GTR_CLK_N2	E28	XCZU3	PS_MGTREFCLK2N_505	C22	GTR Lane 2
GTR_CLK_P2	E27	XCZU3	PS_MGTREFCLK2P_505	C21	GTR Lane 2
GTR_CLK_N3	B30	XCZU3	PS_MGTREFCLK3N_505	A22	GTR Lane 3
GTR_CLK_P3	B29	XCZU3	PS_MGTREFCLK3P_505	A21	GTR Lane 3
PS_MGTRREF	H26	XCZU3	PS_MGTRREF_505	F22	Calibration resistor pin for the termination resistor calibration circuit for the PS-GTR transceivers. Needs to be connected externally. See Schematic Checklist
GTR_RX_N0	K30	XCZU3	PS_MGTRRXN0_505	F28	GTR Lane 0
GTR_RX_N1	J28	XCZU3	PS_MGTRRXN1_505	D28	GTR Lane 1
GTR_RX_N2	D30	XCZU3	PS_MGTRRXN2_505	B28	GTR Lane 2
GTR_RX_N3	C28	XCZU3	PS_MGTRRXN3_505	A26	GTR Lane 3
GTR_RX_P0	K29	XCZU3	PS_MGTRRXP0_505	F27	GTR Lane 0
GTR_RX_P1	J27	XCZU3	PS_MGTRRXP1_505	D27	GTR Lane 1
GTR_RX_P2	D29	XCZU3	PS_MGTRRXP2_505	B27	GTR Lane 2
GTR_RX_P3	C27	XCZU3	PS_MGTRRXP3_505	A25	GTR Lane 3
GTR_TX_N0	M30	XCZU3	PS_MGTRTXN0_505	E26	GTR Lane 0
GTR_TX_N1	G28	XCZU3	PS_MGTRTXN1_505	D24	GTR Lane 1
GTR_TX_N2	F30	XCZU3	PS_MGTRTXN2_505	C26	GTR Lane 2
GTR_TX_N3	A28	XCZU3	PS_MGTRTXN3_505	B24	GTR Lane 3
GTR_TX_P0	M29	XCZU3	PS_MGTRTXP0_505	E25	GTR Lane 0
GTR_TX_P1	G27	XCZU3	PS_MGTRTXP1_505	D23	GTR Lane 1
GTR_TX_P2	F29	XCZU3	PS_MGTRTXP2_505	C25	GTR Lane 2
GTR_TX_P3	A27	XCZU3	PS_MGTRTXP3_505	B23	GTR Lane 3
MIO0	W20	XCZU3	PS_MIO0	AG15
MIO1	W21	XCZU3	PS_MIO1	AG16
MIO10	Y25	XCZU3	PS_MIO10	AD17
MIO11	V24	XCZU3	PS_MIO11	AE17
MIO12	W25	XCZU3	PS_MIO12	AC17
MIO13	Y22	XCZU3	PS_MIO13	AH18
MIO14	Y23	XCZU3	PS_MIO14	AG18
MIO15	W24	XCZU3	PS_MIO15	AE18
MIO16	Y24	XCZU3	PS_MIO16	AF18
MIO17	W26	XCZU3	PS_MIO17	AC18
MIO18	V28	XCZU3	PS_MIO18	AC19
MIO19	Y26	XCZU3	PS_MIO19	AE19
MIO2	V20	XCZU3	PS_MIO2	AF15
MIO20	V27	XCZU3	PS_MIO20	AD19
MIO21	V30	XCZU3	PS_MIO21	AC21
MIO22	V29	XCZU3	PS_MIO22	AB20
MIO23	V25	XCZU3	PS_MIO23	AB18
MIO24	V26	XCZU3	PS_MIO24	AB19
MIO25	U30	XCZU3	PS_MIO25	AB21
MIO26	U21	XCZU3	PS_MIO26	L15
MIO27	T20	XCZU3	PS_MIO27	J15
MIO28	U20	XCZU3	PS_MIO28	K15
MIO29	T19	XCZU3	PS_MIO29	G16
MIO3	Y20	XCZU3	PS_MIO3	AH15
MIO30	R19	XCZU3	PS_MIO30	F16
MIO31	R20	XCZU3	PS_MIO31	H16
MIO32	T21	XCZU3	PS_MIO32	J16
MIO33	U22	XCZU3	PS_MIO33	L16
MIO34	U23	XCZU3	PS_MIO34	L17
MIO35	R21	XCZU3	PS_MIO35	H17
MIO36	T23	XCZU3	PS_MIO36	K17
MIO37	T22	XCZU3	PS_MIO37	J17
MIO38	R22	XCZU3	PS_MIO38	H18
MIO39	R23	XCZU3	PS_MIO39	H19
MIO4	Y21	XCZU3	PS_MIO4	AH16
MIO40	T24	XCZU3	PS_MIO40	K18
MIO41	R24	XCZU3	PS_MIO41	J19
MIO42	U24	XCZU3	PS_MIO42	L18
MIO43	U25	XCZU3	PS_MIO43	K19
MIO44	T25	XCZU3	PS_MIO44	J20
MIO45	T27	XCZU3	PS_MIO45	K20
MIO46	T26	XCZU3	PS_MIO46	L20
MIO47	U26	XCZU3	PS_MIO47	H21
MIO48	T28	XCZU3	PS_MIO48	J21
MIO49	U28	XCZU3	PS_MIO49	M18
MIO5	W23	XCZU3	PS_MIO5	AD16
MIO50	U29	XCZU3	PS_MIO50	M19
MIO51	U27	XCZU3	PS_MIO51	L21
MIO52	P25	XCZU3	PS_MIO52	G18
MIO53	F20	XCZU3	PS_MIO53	D16
MIO54	F21	XCZU3	PS_MIO54	F17
MIO55	E20	XCZU3	PS_MIO55	B16
MIO56	F19	XCZU3	PS_MIO56	C16
MIO57	D20	XCZU3	PS_MIO57	A16
MIO58	L25	XCZU3	PS_MIO58	F18
MIO59	E21	XCZU3	PS_MIO59	E17
MIO6	V21	XCZU3	PS_MIO6	AF16
MIO60	E22	XCZU3	PS_MIO60	C17
MIO61	F22	XCZU3	PS_MIO61	D17
MIO62	D23	XCZU3	PS_MIO62	A17
MIO63	F23	XCZU3	PS_MIO63	E18
MIO64	F24	XCZU3	PS_MIO64	E19
MIO65	A24	XCZU3	PS_MIO65	A18
MIO66	R25	XCZU3	PS_MIO66	G19
MIO67	B24	XCZU3	PS_MIO67	B18
MIO68	D24	XCZU3	PS_MIO68	C18
MIO69	E23	XCZU3	PS_MIO69	D19
MIO7	W22	XCZU3	PS_MIO7	AH17
MIO70	C24	XCZU3	PS_MIO70	C19
MIO71	C25	XCZU3	PS_MIO71	B19
MIO72	P26	XCZU3	PS_MIO72	G20
MIO73	R26	XCZU3	PS_MIO73	G21
MIO74	E24	XCZU3	PS_MIO74	D20
MIO75	A25	XCZU3	PS_MIO75	A19
MIO76	E25	XCZU3	PS_MIO76	B20
MIO77	N25	XCZU3	PS_MIO77	F20
MIO8	V22	XCZU3	PS_MIO8	AF17
MIO9	V23	XCZU3	PS_MIO9	AC16
PS_MODE0	G23	XCZU3	PS_MODE0	P19	4-bit boot mode pins sampled on POR de-assertion
PS_MODE1	G24	XCZU3	PS_MODE1	P20	4-bit boot mode pins sampled on POR de-assertion
PS_MODE2	J23	XCZU3	PS_MODE2	R20	4-bit boot mode pins sampled on POR de-assertion
PS_MODE3	J24	XCZU3	PS_MODE3	T20	4-bit boot mode pins sampled on POR de-assertion
PS_PADI	D26	XCZU3	PS_PADI	N17	Crystal pad input (RTC) 10 Mohm resistor required to be placed between PS_PADI and PS_PADO to use the RTC
PS_PADO	F26	XCZU3	PS_PADO	N18	Crystal pad input (RTC) 10 Mohm resistor required to be placed between PS_PADI and PS_PADO to use the RTC
PS_POR_B	P30	XCZU3	PS_POR_B	P16	Power-on reset signal (connected internally to PGOOD)
PS_PROG_B	P28	XCZU3	PS_PROG_B	R17	PS configuration reset signal
PS_REF_CLK	B26	XCZU3	PS_REF_CLK	R16	System reference clock connected to the output of internal 33MHz oscillator
PS_SRST_B	T29	XCZU3	PS_SRST_B	N19	System reset commonly used during debug
PUDC_B	H22	XCZU3	PUDC_B	U7	Active low input to enable internal pull-ups during configuration on all SelectIO pins. Pin pulled to VCCAUX to disable Weak preconfiguration I/O pull-up resistors
VCC_PSADC	Y29	XCZU3	VCC_PSADC	Y20	PS SYSMON ADC supply voltage
VCC_PSAUX	H24	XCZU3	VCC_PSAUX	U19, U20, V19, W19	Powered by PMIC2 VOUT_A
VCC_PSAUX	N23	XCZU3	VCC_PSAUX	U19, U20, V19, W19	Powered by PMIC2 VOUT_A
VCC_PSBATT	A18	XCZU3	VCC_PSBATT	Y18	Battery Input
VCC_PSDDR_PLL	B18	XCZU3	VCC_PSDDR_PLL	U16, U18	Need to be Connected externally. See Schematic checklist
VCC_PSINTFP	J19	XCZU3	VCC_PSINTFP, VCC_PSINTFP_DDR	AA15, AA16, AA17, AA18, AB16, Y15, Y17, AA20, AA21, Y19	Powered by PMIC2 VOUT_D
VCC_PSINTFP	K19	XCZU3	VCC_PSINTFP, VCC_PSINTFP_DDR	AA15, AA16, AA17, AA18, AB16, Y15, Y17, AA20, AA21, Y19	Powered by PMIC2 VOUT_D
VCC_PSINTLP	L13	XCZU3	VCC_PSINTLP	V16, V17, V18, W15, W16, W17	Powered by PMIC2 VOUT_B
VCC_PSINTLP	M13	XCZU3	VCC_PSINTLP	V16, V17, V18, W15, W16, W17	Powered by PMIC2 VOUT_B
VCC_PSPLL	L17	XCZU3	VCC_PSPLL	T16, T17, T18	Powered by PMIC2 VO_LDO
VCCADC	A20	XCZU3	VCCADC	P12	PL System Monitor supply
VCCADC	B20	XCZU3	VCCADC	P12	PL System Monitor supply
VCCADC	B21	XCZU3	VCCADC	P12	PL System Monitor supply
VCCADC	C20	XCZU3	VCCADC	P12	PL System Monitor supply
VCCADC	D21	XCZU3	VCCADC	P12	PL System Monitor supply
VCCAUX	G22	XCZU3	VCCAUX, VCCAUX_IO	M16, N16, M13, M14, M15	Powered by PMIC1 VOUT_A
VCCAUX	P19	XCZU3	VCCAUX, VCCAUX_IO	M16, N16, M13, M14, M15	Powered by PMIC1 VOUT_A
VCCINT	L11	XCZU3	VCCINT, VCCINT_IO, VCCBRAM	N11, N13, N15, P10, P14, P15, R10, R11, R14, T11, T15, U10, U14, U15, V10, V11, V12, V14, K10, L10, M10, M9, L11, L12, M11, M12	Powered by PMIC1 VOUT_D
VCCINT	M11	XCZU3	VCCINT, VCCINT_IO, VCCBRAM	N11, N13, N15, P10, P14, P15, R10, R11, R14, T11, T15, U10, U14, U15, V10, V11, V12, V14, K10, L10, M10, M9, L11, L12, M11, M12	Powered by PMIC1 VOUT_D
VCCO_HDIO_24	P20	XCZU3	VCCO_24	AA14, AD13	Need to be Connected externally. See Schematic checklist
VCCO_HDIO_25	G20	XCZU3	VCCO_25	B12, E11	Need to be Connected externally. See Schematic Checklist
VCCO_HDIO_26	G21	XCZU3	VCCO_26	C15, F14	Need to be Connected externally. See Schematic Checklist
VCCO_HDIO_44	P18	XCZU3	VCCO_44	AC10, AG12	Need to be Connected externally. See Schematic Checklist
VCCO_HPIO_64	P14	XCZU3	VCCO_64	AC5, AD8, AG7	Need to be Connected externally. See Schematic Checklist
VCCO_HPIO_65	G15	XCZU3	VCCO_65	H5, J3, L4	Need to be Connected externally. See Schematic Checklist
VCCO_HPIO_66	G16	XCZU3	VCCO_66	B7, D3, E6	Need to be Connected externally. See Schematic Checklist
VCCO_PSDDR	L21	XCZU3	VCCO_PSDDR	AB22, AD23, AF24, P23, T24, V25, Y26	Powered by PMIC1 VOUT_C. Only used as a test point
VCCO_PSIO_500	P23	XCZU3	VCCO_PSIO0_500	AB17, AE16, AG17	Need to be Connected externally. Should be connected to either 1.8V or 3.3V depending on the version of the device. See Schematic checklist.
VCCO_PSIO_501	J25	XCZU3	VCCO_PSIO1_501	H20, L19	Need to be Connected externally. See Schematic Checklist
VCCO_PSIO_502	G25	XCZU3	VCCO_PSIO2_502	D18, G17	Need to be Connected externally. See Schematic Checklist
VCCO_PSIO_503	H23	XCZU3	VCCO_PSIO3_503	M17, P18	Need to be Connected externally. See Schematic Checklist
VN	A22	XCZU3	VN	T12	System Monitor dedicated differential analog input. Should be tied to GNDADC if unused
VP	A21	XCZU3	VP	R13	System Monitor dedicated differential analog input. Should be tied to GNDADC if unused
VREF_64	N14	XCZU3	VREF_64	AA7	Need to be Connected externally. See Schematic Checklist
VREF_65	H15	XCZU3	VREF_65	R9	Need to be Connected externally. See Schematic Checklist
VREF_66	H16	XCZU3	VREF_66	G9	Need to be Connected externally. See Schematic Checklist
VREFN	C22	XCZU3	VREFN	R12	Voltage reference GND
VREFP	C21	XCZU3	VREFP	T13	Voltage reference input

Notes:

(1)	See GND pin in XCZU3 Datasheet				A20, A24, A27, A28, AA1, AA19, AA2, AA24, AA3, AA4, AA5, AA6, AA9, AB12, AB27, AC15, AC20, AC25, AD18, AD3, AE1, AE11, AE21, AE26, AE6, AF14, AF19, AF4, AF9, AG2, AG22, AG27, AH5, B17, B2, B21, B25,B26, C10, C20, C24, C27, C28, C5, D13, D21, D26, D8, E16, E20, E24, E27, E28, F19, F21, F25, F26, F4, F9, G12, G2, G22, G23, G24, G27, G28, G7, H10, H15, H25, J13, J18, J23, J8, K11, K16, K21, K26, K6, L24, L9, M1, M2, M22, M27, M3, M4, M5, M7, N10, N12, N14, N20, N25, N5, P11, P3, P5, P8, R1, R15, R2, R21, R26, R5, T10, T14, T19, T3, T5, T9, U1, U11, U17, U2, U22, U27, U6, V13, V15, V3, V7, W1, W18, W2, W23, W6, Y11, Y16, Y3, Y7
(2)	See NC pin in XCZU3 Datasheet				N1, N2, N3, N4, P1, P2, P4, R3, R4, T1, T2, T4, U21, U3, U4, U5, V1, V2, V20, V21, V4, V5, V6, W21, W3, W4, W5, Y1, Y2, Y21, Y4, Y5, Y6

Discrete to OSDZU3 Mapping

Discrete Device	Discrete Signal Name	Discrete Pin Number	SiP Signal Name	SiP Pins	Notes
XCZU3	DXN	U12	DXN	A19	Temperature sensing diode pin
XCZU3	DXP	U13	DXP	B19	Temperature sensing diode pin
XCZU3	GND	A20	VSS	(1)
XCZU3	GND	A24	VSS	(1)
XCZU3	GND	A27	VSS	(1)
XCZU3	GND	A28	VSS	(1)
XCZU3	GND	AA1	VSS	(1)
XCZU3	GND	AA19	VSS	(1)
XCZU3	GND	AA2	VSS	(1)
XCZU3	GND	AA24	VSS	(1)
XCZU3	GND	AA3	VSS	(1)
XCZU3	GND	AA4	VSS	(1)
XCZU3	GND	AA5	VSS	(1)
XCZU3	GND	AA6	VSS	(1)
XCZU3	GND	AA9	VSS	(1)
XCZU3	GND	AB12	VSS	(1)
XCZU3	GND	AB27	VSS	(1)
XCZU3	GND	AC15	VSS	(1)
XCZU3	GND	AC20	VSS	(1)
XCZU3	GND	AC25	VSS	(1)
XCZU3	GND	AD18	VSS	(1)
XCZU3	GND	AD3	VSS	(1)
XCZU3	GND	AE1	VSS	(1)
XCZU3	GND	AE11	VSS	(1)
XCZU3	GND	AE21	VSS	(1)
XCZU3	GND	AE26	VSS	(1)
XCZU3	GND	AE6	VSS	(1)
XCZU3	GND	AF14	VSS	(1)
XCZU3	GND	AF19	VSS	(1)
XCZU3	GND	AF4	VSS	(1)
XCZU3	GND	AF9	VSS	(1)
XCZU3	GND	AG2	VSS	(1)
XCZU3	GND	AG22	VSS	(1)
XCZU3	GND	AG27	VSS	(1)
XCZU3	GND	AH5	VSS	(1)
XCZU3	GND	B17	VSS	(1)
XCZU3	GND	B2	VSS	(1)
XCZU3	GND	B21	VSS	(1)
XCZU3	GND	B25	VSS	(1)
XCZU3	GND	B26	VSS	(1)
XCZU3	GND	C10	VSS	(1)
XCZU3	GND	C20	VSS	(1)
XCZU3	GND	C24	VSS	(1)
XCZU3	GND	C27	VSS	(1)
XCZU3	GND	C28	VSS	(1)
XCZU3	GND	C5	VSS	(1)
XCZU3	GND	D13	VSS	(1)
XCZU3	GND	D21	VSS	(1)
XCZU3	GND	D26	VSS	(1)
XCZU3	GND	D8	VSS	(1)
XCZU3	GND	E16	VSS	(1)
XCZU3	GND	E20	VSS	(1)
XCZU3	GND	E24	VSS	(1)
XCZU3	GND	E27	VSS	(1)
XCZU3	GND	E28	VSS	(1)
XCZU3	GND	F19	VSS	(1)
XCZU3	GND	F21	VSS	(1)
XCZU3	GND	F25	VSS	(1)
XCZU3	GND	F26	VSS	(1)
XCZU3	GND	F4	VSS	(1)
XCZU3	GND	F9	VSS	(1)
XCZU3	GND	G12	VSS	(1)
XCZU3	GND	G2	VSS	(1)
XCZU3	GND	G22	VSS	(1)
XCZU3	GND	G23	VSS	(1)
XCZU3	GND	G24	VSS	(1)
XCZU3	GND	G27	VSS	(1)
XCZU3	GND	G28	VSS	(1)
XCZU3	GND	G7	VSS	(1)
XCZU3	GND	H10	VSS	(1)
XCZU3	GND	H15	VSS	(1)
XCZU3	GND	H25	VSS	(1)
XCZU3	GND	J13	VSS	(1)
XCZU3	GND	J18	VSS	(1)
XCZU3	GND	J23	VSS	(1)
XCZU3	GND	J8	VSS	(1)
XCZU3	GND	K11	VSS	(1)
XCZU3	GND	K16	VSS	(1)
XCZU3	GND	K21	VSS	(1)
XCZU3	GND	K26	VSS	(1)
XCZU3	GND	K6	VSS	(1)
XCZU3	GND	L24	VSS	(1)
XCZU3	GND	L9	VSS	(1)
XCZU3	GND	M1	VSS	(1)
XCZU3	GND	M2	VSS	(1)
XCZU3	GND	M22	VSS	(1)
XCZU3	GND	M27	VSS	(1)
XCZU3	GND	M3	VSS	(1)
XCZU3	GND	M4	VSS	(1)
XCZU3	GND	M5	VSS	(1)
XCZU3	GND	M7	VSS	(1)
XCZU3	GND	N10	VSS	(1)
XCZU3	GND	N12	VSS	(1)
XCZU3	GND	N14	VSS	(1)
XCZU3	GND	N20	VSS	(1)
XCZU3	GND	N25	VSS	(1)
XCZU3	GND	N5	VSS	(1)
XCZU3	GND	P11	VSS	(1)
XCZU3	GND	P3	VSS	(1)
XCZU3	GND	P5	VSS	(1)
XCZU3	GND	P8	VSS	(1)
XCZU3	GND	R1	VSS	(1)
XCZU3	GND	R15	VSS	(1)
XCZU3	GND	R2	VSS	(1)
XCZU3	GND	R21	VSS	(1)
XCZU3	GND	R26	VSS	(1)
XCZU3	GND	R5	VSS	(1)
XCZU3	GND	T10	VSS	(1)
XCZU3	GND	T14	VSS	(1)
XCZU3	GND	T19	VSS	(1)
XCZU3	GND	T3	VSS	(1)
XCZU3	GND	T5	VSS	(1)
XCZU3	GND	T9	VSS	(1)
XCZU3	GND	U1	VSS	(1)
XCZU3	GND	U11	VSS	(1)
XCZU3	GND	U17	VSS	(1)
XCZU3	GND	U2	VSS	(1)
XCZU3	GND	U22	VSS	(1)
XCZU3	GND	U27	VSS	(1)
XCZU3	GND	U6	VSS	(1)
XCZU3	GND	V13	VSS	(1)
XCZU3	GND	V15	VSS	(1)
XCZU3	GND	V3	VSS	(1)
XCZU3	GND	V7	VSS	(1)
XCZU3	GND	W1	VSS	(1)
XCZU3	GND	W18	VSS	(1)
XCZU3	GND	W2	VSS	(1)
XCZU3	GND	W23	VSS	(1)
XCZU3	GND	W6	VSS	(1)
XCZU3	GND	Y11	VSS	(1)
XCZU3	GND	Y16	VSS	(1)
XCZU3	GND	Y3	VSS	(1)
XCZU3	GND	Y7	VSS	(1)
XCZU3	GND_PSADC	W20	GND_PSADC	Y30
XCZU3	GNDADC	P13	GNDADC	A23, B22, B23, C23, D22
XCZU3	IO_L10N_AD10N_24	Y13	24N_L10	T18
XCZU3	IO_L10N_AD10N_25	A10	25N_L10	C11
XCZU3	IO_L10N_AD2N_26	H13	26N_L10	F16
XCZU3	IO_L10N_AD2N_44	Y10	44N_L10	R12
XCZU3	IO_L10N_T1U_N7_QBC_AD4N_64	AG5	64N_L10	Y8
XCZU3	IO_L10N_T1U_N7_QBC_AD4N_65	H3	65N_L10	K4
XCZU3	IO_L10N_T1U_N7_QBC_AD4N_66	A4	66N_L10	B3
XCZU3	IO_L10P_AD10P_24	Y14	24P_L10	T17
XCZU3	IO_L10P_AD10P_25	B11	25P_L10	B11
XCZU3	IO_L10P_AD2P_26	H14	26P_L10	F15
XCZU3	IO_L10P_AD2P_44	W10	44P_L10	R11
XCZU3	IO_L10P_T1U_N6_QBC_AD4P_64	AG6	64P_L10	W8
XCZU3	IO_L10P_T1U_N6_QBC_AD4P_65	H4	65P_L10	J4
XCZU3	IO_L10P_T1U_N6_QBC_AD4P_66	B4	66P_L10	A3
XCZU3	IO_L11N_AD1N_26	J14	26N_L11	E19
XCZU3	IO_L11N_AD1N_44	AA8	44N_L11	R14
XCZU3	IO_L11N_AD9N_24	W11	24N_L11	R16
XCZU3	IO_L11N_AD9N_25	A11	25N_L11	A13
XCZU3	IO_L11N_T1U_N9_GC_64	AF6	64N_L11	T10
XCZU3	IO_L11N_T1U_N9_GC_65	K3	65N_L11	M4
XCZU3	IO_L11N_T1U_N9_GC_66	C4	66N_L11	D4
XCZU3	IO_L11P_AD1P_26	K14	26P_L11	E18
XCZU3	IO_L11P_AD1P_44	Y9	44P_L11	R13
XCZU3	IO_L11P_AD9P_24	W12	24P_L11	R15
XCZU3	IO_L11P_AD9P_25	A12	25P_L11	A12
XCZU3	IO_L11P_T1U_N8_GC_64	AF7	64P_L11	R10
XCZU3	IO_L11P_T1U_N8_GC_65	K4	65P_L11	L4
XCZU3	IO_L11P_T1U_N8_GC_66	D4	66P_L11	C4
XCZU3	IO_L12N_AD0N_26	L13	26N_L12	F18
XCZU3	IO_L12N_AD0N_44	AB9	44N_L12	T14
XCZU3	IO_L12N_AD8N_24	AA12	24N_L12	T16
XCZU3	IO_L12N_AD8N_25	C12	25N_L12	B13
XCZU3	IO_L12N_T1U_N11_GC_64	AF5	64N_L12	V10
XCZU3	IO_L12N_T1U_N11_GC_65	L2	65N_L12	R2
XCZU3	IO_L12N_T1U_N11_GC_66	C2	66N_L12	E2
XCZU3	IO_L12P_AD0P_26	L14	26P_L12	F17
XCZU3	IO_L12P_AD0P_44	AB10	44P_L12	T13
XCZU3	IO_L12P_AD8P_24	Y12	24P_L12	T15
XCZU3	IO_L12P_AD8P_25	D12	25P_L12	B12
XCZU3	IO_L12P_T1U_N10_GC_64	AE5	64P_L12	U10
XCZU3	IO_L12P_T1U_N10_GC_65	L3	65P_L12	P2
XCZU3	IO_L12P_T1U_N10_GC_66	C3	66P_L12	D2
XCZU3	IO_L13N_T2L_N1_GC_QBC_64	AD4	64N_L13	V7
XCZU3	IO_L13N_T2L_N1_GC_QBC_65	L6	65N_L13	H5
XCZU3	IO_L13N_T2L_N1_GC_QBC_66	D6	66N_L13	B8
XCZU3	IO_L13P_T2L_N0_GC_QBC_64	AD5	64P_L13	U7
XCZU3	IO_L13P_T2L_N0_GC_QBC_65	L7	65P_L13	G5
XCZU3	IO_L13P_T2L_N0_GC_QBC_66	D7	66P_L13	A8
XCZU3	IO_L14N_T2L_N3_GC_64	AC3	64N_L14	V5
XCZU3	IO_L14N_T2L_N3_GC_65	L5	65N_L14	F5
XCZU3	IO_L14N_T2L_N3_GC_66	D5	66N_L14	F4
XCZU3	IO_L14P_T2L_N2_GC_64	AC4	64P_L14	U5
XCZU3	IO_L14P_T2L_N2_GC_65	M6	65P_L14	E5
XCZU3	IO_L14P_T2L_N2_GC_66	E5	66P_L14	E4
XCZU3	IO_L15N_T2L_N5_AD11N_64	AB3	64N_L15	V6
XCZU3	IO_L15N_T2L_N5_AD11N_65	N6	65N_L15	T4
XCZU3	IO_L15N_T2L_N5_AD11N_66	F6	66N_L15	D8
XCZU3	IO_L15P_T2L_N4_AD11P_64	AB4	64P_L15	U6
XCZU3	IO_L15P_T2L_N4_AD11P_65	N7	65P_L15	R4
XCZU3	IO_L15P_T2L_N4_AD11P_66	G6	66P_L15	C8
XCZU3	IO_L16N_T2U_N7_QBC_AD3N_64	AD1	64N_L16	W2
XCZU3	IO_L16N_T2U_N7_QBC_AD3N_65	P6	65N_L16	V4
XCZU3	IO_L16N_T2U_N7_QBC_AD3N_66	F7	66N_L16	F10
XCZU3	IO_L16P_T2U_N6_QBC_AD3P_64	AD2	64P_L16	V2
XCZU3	IO_L16P_T2U_N6_QBC_AD3P_65	P7	65P_L16	U4
XCZU3	IO_L16P_T2U_N6_QBC_AD3P_66	G8	66P_L16	E10
XCZU3	IO_L17N_T2U_N9_AD10N_64	AC2	64N_L17	U2
XCZU3	IO_L17N_T2U_N9_AD10N_65	N8	65N_L17	K6
XCZU3	IO_L17N_T2U_N9_AD10N_66	E8	66N_L17	D10
XCZU3	IO_L17P_T2U_N8_AD10P_64	AB2	64P_L17	T2
XCZU3	IO_L17P_T2U_N8_AD10P_65	N9	65P_L17	J6
XCZU3	IO_L17P_T2U_N8_AD10P_66	F8	66P_L17	C10
XCZU3	IO_L18N_T2U_N11_AD2N_64	AC1	64N_L18	T1
XCZU3	IO_L18N_T2U_N11_AD2N_65	L8	65N_L18	H6
XCZU3	IO_L18N_T2U_N11_AD2N_66	D9	66N_L18	B10
XCZU3	IO_L18P_T2U_N10_AD2P_64	AB1	64P_L18	R1
XCZU3	IO_L18P_T2U_N10_AD2P_65	M8	65P_L18	G6
XCZU3	IO_L18P_T2U_N10_AD2P_66	E9	66P_L18	A10
XCZU3	IO_L19N_T3L_N1_DBC_AD9N_64	AH4	64N_L19	Y7
XCZU3	IO_L19N_T3L_N1_DBC_AD9N_65	J4	65N_L19	B6
XCZU3	IO_L19N_T3L_N1_DBC_AD9N_66	A5	66N_L19	B4
XCZU3	IO_L19P_T3L_N0_DBC_AD9P_64	AG4	64P_L19	W7
XCZU3	IO_L19P_T3L_N0_DBC_AD9P_65	J5	65P_L19	A6
XCZU3	IO_L19P_T3L_N0_DBC_AD9P_66	B5	66P_L19	A4
XCZU3	IO_L1N_AD11N_26	A15	26N_L1	A17
XCZU3	IO_L1N_AD11N_44	AH10	44N_L1	Y13
XCZU3	IO_L1N_AD15N_24	AE14	24N_L1	W19
XCZU3	IO_L1N_AD15N_25	J10	25N_L1	F12
XCZU3	IO_L1N_T0L_N1_DBC_64	AD9	64N_L1	V9
XCZU3	IO_L1N_T0L_N1_DBC_65	Y8	65N_L1	T6
XCZU3	IO_L1N_T0L_N1_DBC_66	F1	66N_L1	K1
XCZU3	IO_L1P_AD11P_26	B15	26P_L1	A16
XCZU3	IO_L1P_AD11P_44	AG10	44P_L1	Y12
XCZU3	IO_L1P_AD15P_24	AE15	24P_L1	W18
XCZU3	IO_L1P_AD15P_25	J11	25P_L1	F11
XCZU3	IO_L1P_T0L_N0_DBC_64	AC9	64P_L1	U9
XCZU3	IO_L1P_T0L_N0_DBC_65	W8	65P_L1	R6
XCZU3	IO_L1P_T0L_N0_DBC_66	G1	66P_L1	J1
XCZU3	IO_L20N_T3L_N3_AD1N_64	AH3	64N_L20	Y6
XCZU3	IO_L20N_T3L_N3_AD1N_65	H6	65N_L20	F8
XCZU3	IO_L20N_T3L_N3_AD1N_66	B6	66N_L20	F7
XCZU3	IO_L20P_T3L_N2_AD1P_64	AG3	64P_L20	W6
XCZU3	IO_L20P_T3L_N2_AD1P_65	J6	65P_L20	E8
XCZU3	IO_L20P_T3L_N2_AD1P_66	C6	66P_L20	E7
XCZU3	IO_L21N_T3L_N5_AD8N_64	AF3	64N_L21	Y5
XCZU3	IO_L21N_T3L_N5_AD8N_65	H7	65N_L21	D5
XCZU3	IO_L21N_T3L_N5_AD8N_66	A6	66N_L21	B7
XCZU3	IO_L21P_T3L_N4_AD8P_64	AE3	64P_L21	W5
XCZU3	IO_L21P_T3L_N4_AD8P_65	J7	65P_L21	C5
XCZU3	IO_L21P_T3L_N4_AD8P_66	A7	66P_L21	A7
XCZU3	IO_L22N_T3U_N7_DBC_AD0N_64	AF2	64N_L22	Y4
XCZU3	IO_L22N_T3U_N7_DBC_AD0N_65	K7	65N_L22	P4
XCZU3	IO_L22N_T3U_N7_DBC_AD0N_66	B8	66N_L22	F9
XCZU3	IO_L22P_T3U_N6_DBC_AD0P_64	AE2	64P_L22	W4
XCZU3	IO_L22P_T3U_N6_DBC_AD0P_65	K8	65P_L22	N4
XCZU3	IO_L22P_T3U_N6_DBC_AD0P_66	C8	66P_L22	E9
XCZU3	IO_L23N_T3U_N9_64	AH1	64N_L23	Y3
XCZU3	IO_L23N_T3U_N9_65	J9	65N_L23	F6
XCZU3	IO_L23N_T3U_N9_66	A8	66N_L23	B9
XCZU3	IO_L23P_T3U_N8_64	AH2	64P_L23	W3
XCZU3	IO_L23P_T3U_N8_66	A9	66P_L23	A9
XCZU3	IO_L23P_T3U_N8_I2C_SCLK_65	K9	65P_L23	E6
XCZU3	IO_L24N_T3U_N11_64	AG1	64N_L24	V1
XCZU3	IO_L24N_T3U_N11_66	B9	66N_L24	D9
XCZU3	IO_L24N_T3U_N11_PERSTN0_65	H8	65N_L24	D6
XCZU3	IO_L24P_T3U_N10_64	AF1	64P_L24	U1
XCZU3	IO_L24P_T3U_N10_66	C9	66P_L24	C9
XCZU3	IO_L24P_T3U_N10_PERSTN1_I2C_SDA_65	H9	65P_L24	C6
XCZU3	IO_L2N_AD10N_26	A14	26N_L2	B15
XCZU3	IO_L2N_AD10N_44	AG11	44N_L2	W15
XCZU3	IO_L2N_AD14N_24	AH14	24N_L2	Y19
XCZU3	IO_L2N_AD14N_25	K12	25N_L2	F14
XCZU3	IO_L2N_T0L_N3_64	AE8	64N_L2	V11
XCZU3	IO_L2N_T0L_N3_65	V9	65N_L2	T5
XCZU3	IO_L2N_T0L_N3_66	D1	66N_L2	H1
XCZU3	IO_L2P_AD10P_26	B14	26P_L2	B14
XCZU3	IO_L2P_AD10P_44	AF11	44P_L2	W14
XCZU3	IO_L2P_AD14P_24	AG14	24P_L2	Y18
XCZU3	IO_L2P_AD14P_25	K13	25P_L2	F13
XCZU3	IO_L2P_T0L_N2_64	AE9	64P_L2	U11
XCZU3	IO_L2P_T0L_N2_65	U9	65P_L2	R5
XCZU3	IO_L2P_T0L_N2_66	E1	66P_L2	G1
XCZU3	IO_L3N_AD13N_24	AH13	24N_L3	Y17
XCZU3	IO_L3N_AD13N_25	G10	25N_L3	E13
XCZU3	IO_L3N_AD9N_26	A13	26N_L3	A15
XCZU3	IO_L3N_AD9N_44	AH11	44N_L3	Y15
XCZU3	IO_L3N_T0L_N5_AD15N_64	AC8	64N_L3	T9
XCZU3	IO_L3N_T0L_N5_AD15N_65	V8	65N_L3	P6
XCZU3	IO_L3N_T0L_N5_AD15N_66	E2	66N_L3	L2
XCZU3	IO_L3P_AD13P_24	AG13	24P_L3	Y16
XCZU3	IO_L3P_AD13P_25	H11	25P_L3	E12
XCZU3	IO_L3P_AD9P_26	B13	26P_L3	A14
XCZU3	IO_L3P_AD9P_44	AH12	44P_L3	Y14
XCZU3	IO_L3P_T0L_N4_AD15P_64	AB8	64P_L3	R9
XCZU3	IO_L3P_T0L_N4_AD15P_65	U8	65P_L3	N6
XCZU3	IO_L3P_T0L_N4_AD15P_66	F2	66P_L3	K2
XCZU3	IO_L4N_AD12N_24	AF13	24N_L4	W17
XCZU3	IO_L4N_AD12N_25	H12	25N_L4	D13
XCZU3	IO_L4N_AD8N_26	C13	26N_L4	B17
XCZU3	IO_L4N_AD8N_44	AF10	44N_L4	W13
XCZU3	IO_L4N_T0U_N7_DBC_AD7N_64	AE7	64N_L4	V8
XCZU3	IO_L4N_T0U_N7_DBC_AD7N_65	T8	65N_L4	P5
XCZU3	IO_L4N_T0U_N7_DBC_AD7N_66	F3	66N_L4	J2
XCZU3	IO_L4P_AD12P_24	AE13	24P_L4	W16
XCZU3	IO_L4P_AD12P_25	J12	25P_L4	D12
XCZU3	IO_L4P_AD8P_26	C14	26P_L4	B16
XCZU3	IO_L4P_AD8P_44	AE10	44P_L4	W12
XCZU3	IO_L4P_T0U_N6_DBC_AD7P_64	AD7	64P_L4	U8
XCZU3	IO_L4P_T0U_N6_DBC_AD7P_66	G3	66P_L4	H2
XCZU3	IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65	R8	65P_L4	N5
XCZU3	IO_L5N_HDGC_24	AD14	24N_L5	V19
XCZU3	IO_L5N_HDGC_25	F10	25N_L5	C13
XCZU3	IO_L5N_HDGC_AD7N_26	D14	26N_L5	C17
XCZU3	IO_L5N_HDGC_AD7N_44	AF12	44N_L5	V15
XCZU3	IO_L5N_T0U_N9_AD14N_64	AC7	64N_L5	T8
XCZU3	IO_L5N_T0U_N9_AD14N_65	T7	65N_L5	M6
XCZU3	IO_L5N_T0U_N9_AD14N_66	E3	66N_L5	G2
XCZU3	IO_L5P_HDGC_24	AD15	24P_L5	V18
XCZU3	IO_L5P_HDGC_25	G11	25P_L5	C12
XCZU3	IO_L5P_HDGC_AD7P_26	D15	26P_L5	C16
XCZU3	IO_L5P_HDGC_AD7P_44	AE12	44P_L5	V14
XCZU3	IO_L5P_T0U_N8_AD14P_64	AB7	64P_L5	R8
XCZU3	IO_L5P_T0U_N8_AD14P_65	R7	65P_L5	L6
XCZU3	IO_L5P_T0U_N8_AD14P_66	E4	66P_L5	F2
XCZU3	IO_L6N_HDGC_24	AC13	24N_L6	V17
XCZU3	IO_L6N_HDGC_25	F11	25N_L6	D15
XCZU3	IO_L6N_HDGC_AD6N_26	E13	26N_L6	D17
XCZU3	IO_L6N_HDGC_AD6N_44	AD12	44N_L6	U15
XCZU3	IO_L6N_T0U_N11_AD6N_64	AC6	64N_L6	T7
XCZU3	IO_L6N_T0U_N11_AD6N_65	T6	65N_L6	M5
XCZU3	IO_L6N_T0U_N11_AD6N_66	F5	66N_L6	H4
XCZU3	IO_L6P_HDGC_24	AC14	24P_L6	V16
XCZU3	IO_L6P_HDGC_25	F12	25P_L6	D14
XCZU3	IO_L6P_HDGC_AD6P_26	E14	26P_L6	D16
XCZU3	IO_L6P_HDGC_AD6P_44	AC12	44P_L6	U14
XCZU3	IO_L6P_T0U_N10_AD6P_64	AB6	64P_L6	R7
XCZU3	IO_L6P_T0U_N10_AD6P_65	R6	65P_L6	L5
XCZU3	IO_L6P_T0U_N10_AD6P_66	G5	66P_L6	G4
XCZU3	IO_L7N_HDGC_24	AB13	24N_L7	U17
XCZU3	IO_L7N_HDGC_25	D10	25N_L7	E15
XCZU3	IO_L7N_HDGC_AD5N_26	F13	26N_L7	C19
XCZU3	IO_L7N_HDGC_AD5N_44	AD10	44N_L7	V13
XCZU3	IO_L7N_T1L_N1_QBC_AD13N_64	AH9	64N_L7	Y11
XCZU3	IO_L7N_T1L_N1_QBC_AD13N_65	K1	65N_L7	P1
XCZU3	IO_L7N_T1L_N1_QBC_AD13N_66	B1	66N_L7	F1
XCZU3	IO_L7P_HDGC_24	AA13	24P_L7	U16
XCZU3	IO_L7P_HDGC_25	E10	25P_L7	E14
XCZU3	IO_L7P_HDGC_AD5P_26	G13	26P_L7	C18
XCZU3	IO_L7P_HDGC_AD5P_44	AD11	44P_L7	V12
XCZU3	IO_L7P_T1L_N0_QBC_AD13P_64	AG9	64P_L7	W11
XCZU3	IO_L7P_T1L_N0_QBC_AD13P_65	L1	65P_L7	N1
XCZU3	IO_L7P_T1L_N0_QBC_AD13P_66	C1	66P_L7	E1
XCZU3	IO_L8N_HDGC_24	AB14	24N_L8	U19
XCZU3	IO_L8N_HDGC_25	D11	25N_L8	C15
XCZU3	IO_L8N_HDGC_AD4N_26	E15	26N_L8	D19
XCZU3	IO_L8N_HDGC_AD4N_44	AC11	44N_L8	U13
XCZU3	IO_L8N_T1L_N3_AD5N_64	AG8	64N_L8	Y9
XCZU3	IO_L8N_T1L_N3_AD5N_65	H1	65N_L8	M1
XCZU3	IO_L8N_T1L_N3_AD5N_66	A1	66N_L8	D1
XCZU3	IO_L8P_HDGC_24	AB15	24P_L8	U18
XCZU3	IO_L8P_HDGC_25	E12	25P_L8	C14
XCZU3	IO_L8P_HDGC_AD4P_26	F15	26P_L8	D18
XCZU3	IO_L8P_HDGC_AD4P_44	AB11	44P_L8	U12
XCZU3	IO_L8P_T1L_N2_AD5P_64	AF8	64P_L8	W9
XCZU3	IO_L8P_T1L_N2_AD5P_65	J1	65P_L8	L1
XCZU3	IO_L8P_T1L_N2_AD5P_66	A2	66P_L8	C1
XCZU3	IO_L9N_AD11N_24	W13	24N_L9	R18
XCZU3	IO_L9N_AD11N_25	B10	25N_L9	E11
XCZU3	IO_L9N_AD3N_26	G14	26N_L9	E17
XCZU3	IO_L9N_AD3N_44	AA10	44N_L9	T12
XCZU3	IO_L9N_T1L_N5_AD12N_64	AH7	64N_L9	Y10
XCZU3	IO_L9N_T1L_N5_AD12N_65	J2	65N_L9	N2
XCZU3	IO_L9N_T1L_N5_AD12N_66	A3	66N_L9	C2
XCZU3	IO_L9P_AD11P_24	W14	24P_L9	R17
XCZU3	IO_L9P_AD11P_25	C11	25P_L9	D11
XCZU3	IO_L9P_AD3P_26	G15	26P_L9	E16
XCZU3	IO_L9P_AD3P_44	AA11	44P_L9	T11
XCZU3	IO_L9P_T1L_N4_AD12P_64	AH8	64P_L9	W10
XCZU3	IO_L9P_T1L_N4_AD12P_65	K2	65P_L9	M2
XCZU3	IO_L9P_T1L_N4_AD12P_66	B3	66P_L9	B2
XCZU3	IO_T0U_N12_VRP_64	AD6	64_T0	J5
XCZU3	IO_T0U_N12_VRP_65	W9	65_T0	P3
XCZU3	IO_T0U_N12_VRP_66	G4	66_T0	F3
XCZU3	IO_T1U_N12_64	AH6	64_T1	V3
XCZU3	IO_T1U_N12_65	H2	65_T1	G3
XCZU3	IO_T1U_N12_66	D2	66_T1	C3
XCZU3	IO_T2U_N12_64	AB5	64_T2	R3
XCZU3	IO_T2U_N12_65	P9	65_T2	B5
XCZU3	IO_T2U_N12_66	E7	66_T2	D7
XCZU3	IO_T3U_N12_64	AE4	64_T3	K5
XCZU3	IO_T3U_N12_65	K5	65_T3	A5
XCZU3	IO_T3U_N12_66	C7	66_T3	C7
XCZU3	NC	N1		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	N2		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	N3		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	N4		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	P1		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	P2		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	P4		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	R3		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	R4		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	T1		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	T2		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	T4		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	U3		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	U4		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	U5		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	V1		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	V2		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	V4		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	V5		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	V6		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	W3		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	W4		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	W5		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	Y1		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	Y2		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	Y4		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	Y5		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	NC	Y6		(2)	This signal is not brought out to the boundary of the SiP
XCZU3	POR_OVERRIDE	W7	POR_OVERRIDE	J22	Power on reset delay override. Pulled low to GND to set standard PL power on delay time
XCZU3	PS_DDR_A0	W28			This signal is connected internally within the SiP
XCZU3	PS_DDR_A1	Y28			This signal is connected internally within the SiP
XCZU3	PS_DDR_A10	AA25			This signal is connected internally within the SiP
XCZU3	PS_DDR_A11	AA26			This signal is connected internally within the SiP
XCZU3	PS_DDR_A12	AB25			This signal is connected internally within the SiP
XCZU3	PS_DDR_A13	AB26			This signal is connected internally within the SiP
XCZU3	PS_DDR_A14	AB24			This signal is connected internally within the SiP
XCZU3	PS_DDR_A15	AC24			This signal is connected internally within the SiP
XCZU3	PS_DDR_A16	AC23			This signal is connected internally within the SiP
XCZU3	PS_DDR_A17	AC22			This signal is connected internally within the SiP
XCZU3	PS_DDR_A2	AB28			This signal is connected internally within the SiP
XCZU3	PS_DDR_A3	AA28			This signal is connected internally within the SiP
XCZU3	PS_DDR_A4	Y27			This signal is connected internally within the SiP
XCZU3	PS_DDR_A5	AA27			This signal is connected internally within the SiP
XCZU3	PS_DDR_A6	Y22			This signal is connected internally within the SiP
XCZU3	PS_DDR_A7	AA23			This signal is connected internally within the SiP
XCZU3	PS_DDR_A8	AA22			This signal is connected internally within the SiP
XCZU3	PS_DDR_A9	AB23			This signal is connected internally within the SiP
XCZU3	PS_DDR_ACT_N	Y23			This signal is connected internally within the SiP
XCZU3	PS_DDR_ALERT_N	U25			This signal is connected internally within the SiP
XCZU3	PS_DDR_BA0	V23			This signal is connected internally within the SiP
XCZU3	PS_DDR_BA1	W22			This signal is connected internally within the SiP
XCZU3	PS_DDR_BG0	W24			This signal is connected internally within the SiP
XCZU3	PS_DDR_BG1	V22			This signal is connected internally within the SiP
XCZU3	PS_DDR_CK_N0	W26			This signal is connected internally within the SiP
XCZU3	PS_DDR_CK_N1	Y25			This signal is connected internally within the SiP
XCZU3	PS_DDR_CK0	W25			This signal is connected internally within the SiP
XCZU3	PS_DDR_CK1	Y24			This signal is connected internally within the SiP
XCZU3	PS_DDR_CKE0	V28			This signal is connected internally within the SiP
XCZU3	PS_DDR_CKE1	V27			This signal is connected internally within the SiP
XCZU3	PS_DDR_CS_N0	W27			This signal is connected internally within the SiP
XCZU3	PS_DDR_CS_N1	V26			This signal is connected internally within the SiP
XCZU3	PS_DDR_DM0	AG20			This signal is connected internally within the SiP
XCZU3	PS_DDR_DM1	AE23			This signal is connected internally within the SiP
XCZU3	PS_DDR_DM2	AE25			This signal is connected internally within the SiP
XCZU3	PS_DDR_DM3	AE28			This signal is connected internally within the SiP
XCZU3	PS_DDR_DM4	R23			This signal is connected internally within the SiP
XCZU3	PS_DDR_DM5	H23			This signal is connected internally within the SiP
XCZU3	PS_DDR_DM6	L27			This signal is connected internally within the SiP
XCZU3	PS_DDR_DM7	H26			This signal is connected internally within the SiP
XCZU3	PS_DDR_DM8	T26			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ0	AD21			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ1	AE20			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ10	AE22			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ11	AD22			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ12	AH23			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ13	AH24			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ14	AE24			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ15	AG24			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ16	AC26			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ17	AD26			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ18	AD25			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ19	AD24			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ2	AD20			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ20	AG26			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ21	AH25			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ22	AH26			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ23	AG25			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ24	AH27			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ25	AH28			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ26	AF28			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ27	AG28			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ28	AC27			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ29	AD27			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ3	AF20			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ30	AD28			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ31	AC28			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ32	T22			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ33	R22			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ34	P22			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ35	N22			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ36	T23			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ37	P24			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ38	R24			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ39	N24			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ4	AH21			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ40	H24			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ41	J24			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ42	M24			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ43	K24			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ44	J22			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ45	H22			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ46	K22			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ47	L22			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ48	M25			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ49	M26			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ5	AH20			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ50	L25			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ51	L26			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ52	K28			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ53	L28			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ54	M28			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ55	N28			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ56	J28			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ57	K27			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ58	H28			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ59	H27			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ6	AH19			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ60	G26			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ61	G25			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ62	K25			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ63	J25			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ64	T28			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ65	R28			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ66	P28			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ67	P27			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ68	P26			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ69	R25			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ7	AG19			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ70	P25			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ71	T25			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ8	AF22			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQ9	AH22			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQS_N0	AG21			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQS_N1	AG23			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQS_N2	AF26			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQS_N3	AF27			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQS_N4	M23			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQS_N5	K23			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQS_N6	N27			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQS_N7	J27			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQS_N8	T27			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQS_P0	AF21			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQS_P1	AF23			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQS_P2	AF25			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQS_P3	AE27			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQS_P4	N23			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQS_P5	L23			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQS_P6	N26			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQS_P7	J26			This signal is connected internally within the SiP
XCZU3	PS_DDR_DQS_P8	R27			This signal is connected internally within the SiP
XCZU3	PS_DDR_ODT0	U28			This signal is connected internally within the SiP
XCZU3	PS_DDR_ODT1	U26			This signal is connected internally within the SiP
XCZU3	PS_DDR_PARITY	V24			This signal is connected internally within the SiP
XCZU3	PS_DDR_RAM_RST_N	U23			This signal is connected internally within the SiP
XCZU3	PS_DDR_ZQ	U24			This signal is connected internally within the SiP
XCZU3	PS_DONE	M21	PS_DONE	N28	Indicates the PS configuration is completed
XCZU3	PS_ERROR_OUT	P17	PS_ERR_OUT	L3	Asserted for accidental loss of power, a hardware error, or an exception in the PMU
XCZU3	PS_ERROR_STATUS	M20	PS_ERR_STAT	M3	Indicates a secure lockdown state. Alternatively, it can be used by the PMU firmware to indicate system status
XCZU3	PS_INIT_B	P21	PS_INIT_B	P29	Indicates the PL is initialized after a power-on reset (POR). This signal should not be held Low externally to delay the PL configuration sequence because the signal level is not visible to software. However, if there is a CRC error detected when the PL bit stream is loaded PS_INIT_B will be driven low
XCZU3	PS_JTAG_TCK	R19	PS_TCK	T30	JTAG
XCZU3	PS_JTAG_TDI	R18	PS_TDI	R29	JTAG
XCZU3	PS_JTAG_TDO	T21	PS_TDO	R30	JTAG
XCZU3	PS_JTAG_TMS	N21	PS_TMS	R28	JTAG
XCZU3	PS_MGTRAVCC	B22	+MGTRAVCC	K26	Powered by LDO2. Test point for internal power supply for GTRs
XCZU3	PS_MGTRAVCC	D22	+MGTRAVCC	K26	Powered by LDO2. Test point for internal power supply for GTRs
XCZU3	PS_MGTRAVTT	A23	+MGTRAVTT	M26	Powered by PMIC1 VO_LDO. Test point for internal power supply for GTRs
XCZU3	PS_MGTRAVTT	C23	+MGTRAVTT	M26	Powered by PMIC1 VO_LDO. Test point for internal power supply for GTRs
XCZU3	PS_MGTRAVTT	D25	+MGTRAVTT	M26	Powered by PMIC1 VO_LDO. Test point for internal power supply for GTRs
XCZU3	PS_MGTRAVTT	E23	+MGTRAVTT	M26	Powered by PMIC1 VO_LDO. Test point for internal power supply for GTRs
XCZU3	PS_MGTREFCLK0N_505	F24	GTR_CLK_N0	L28	GTR Lane 0
XCZU3	PS_MGTREFCLK0P_505	F23	GTR_CLK_P0	L27	GTR Lane 1
XCZU3	PS_MGTREFCLK1N_505	E22	GTR_CLK_N1	H30	GTR Lane 2
XCZU3	PS_MGTREFCLK1P_505	E21	GTR_CLK_P1	H29	GTR Lane 3
XCZU3	PS_MGTREFCLK2N_505	C22	GTR_CLK_N2	E28	GTR Lane 0
XCZU3	PS_MGTREFCLK2P_505	C21	GTR_CLK_P2	E27	GTR Lane 1
XCZU3	PS_MGTREFCLK3N_505	A22	GTR_CLK_N3	B30	GTR Lane 2
XCZU3	PS_MGTREFCLK3P_505	A21	GTR_CLK_P3	B29	GTR Lane 3
XCZU3	PS_MGTRREF_505	F22	PS_MGTRREF	H26	Calibration resistor pin for the termination resistor calibration circuit for the PS-GTR transceivers. Needs to be connected externally. See Schematic Checklist
XCZU3	PS_MGTRRXN0_505	F28	GTR_RX_N0	K30	GTR Lane 0
XCZU3	PS_MGTRRXN1_505	D28	GTR_RX_N1	J28	GTR Lane 1
XCZU3	PS_MGTRRXN2_505	B28	GTR_RX_N2	D30	GTR Lane 2
XCZU3	PS_MGTRRXN3_505	A26	GTR_RX_N3	C28	GTR Lane 3
XCZU3	PS_MGTRRXP0_505	F27	GTR_RX_P0	K29	GTR Lane 0
XCZU3	PS_MGTRRXP1_505	D27	GTR_RX_P1	J27	GTR Lane 1
XCZU3	PS_MGTRRXP2_505	B27	GTR_RX_P2	D29	GTR Lane 2
XCZU3	PS_MGTRRXP3_505	A25	GTR_RX_P3	C27	GTR Lane 3
XCZU3	PS_MGTRTXN0_505	E26	GTR_TX_N0	M30	GTR Lane 0
XCZU3	PS_MGTRTXN1_505	D24	GTR_TX_N1	G28	GTR Lane 1
XCZU3	PS_MGTRTXN2_505	C26	GTR_TX_N2	F30	GTR Lane 2
XCZU3	PS_MGTRTXN3_505	B24	GTR_TX_N3	A28	GTR Lane 3
XCZU3	PS_MGTRTXP0_505	E25	GTR_TX_P0	M29	GTR Lane 0
XCZU3	PS_MGTRTXP1_505	D23	GTR_TX_P1	G27	GTR Lane 1
XCZU3	PS_MGTRTXP2_505	C25	GTR_TX_P2	F29	GTR Lane 2
XCZU3	PS_MGTRTXP3_505	B23	GTR_TX_P3	A27	GTR Lane 3
XCZU3	PS_MIO0	AG15	MIO0	W20
XCZU3	PS_MIO1	AG16	MIO1	W21
XCZU3	PS_MIO10	AD17	MIO10	Y25
XCZU3	PS_MIO11	AE17	MIO11	V24
XCZU3	PS_MIO12	AC17	MIO12	W25
XCZU3	PS_MIO13	AH18	MIO13	Y22
XCZU3	PS_MIO14	AG18	MIO14	Y23
XCZU3	PS_MIO15	AE18	MIO15	W24
XCZU3	PS_MIO16	AF18	MIO16	Y24
XCZU3	PS_MIO17	AC18	MIO17	W26
XCZU3	PS_MIO18	AC19	MIO18	V28
XCZU3	PS_MIO19	AE19	MIO19	Y26
XCZU3	PS_MIO2	AF15	MIO2	V20
XCZU3	PS_MIO20	AD19	MIO20	V27
XCZU3	PS_MIO21	AC21	MIO21	V30
XCZU3	PS_MIO22	AB20	MIO22	V29
XCZU3	PS_MIO23	AB18	MIO23	V25
XCZU3	PS_MIO24	AB19	MIO24	V26
XCZU3	PS_MIO25	AB21	MIO25	U30
XCZU3	PS_MIO26	L15	MIO26	U21
XCZU3	PS_MIO27	J15	MIO27	T20
XCZU3	PS_MIO28	K15	MIO28	U20
XCZU3	PS_MIO29	G16	MIO29	T19
XCZU3	PS_MIO3	AH15	MIO3	Y20
XCZU3	PS_MIO30	F16	MIO30	R19
XCZU3	PS_MIO31	H16	MIO31	R20
XCZU3	PS_MIO32	J16	MIO32	T21
XCZU3	PS_MIO33	L16	MIO33	U22
XCZU3	PS_MIO34	L17	MIO34	U23
XCZU3	PS_MIO35	H17	MIO35	R21
XCZU3	PS_MIO36	K17	MIO36	T23
XCZU3	PS_MIO37	J17	MIO37	T22
XCZU3	PS_MIO38	H18	MIO38	R22
XCZU3	PS_MIO39	H19	MIO39	R23
XCZU3	PS_MIO4	AH16	MIO4	Y21
XCZU3	PS_MIO40	K18	MIO40	T24
XCZU3	PS_MIO41	J19	MIO41	R24
XCZU3	PS_MIO42	L18	MIO42	U24
XCZU3	PS_MIO43	K19	MIO43	U25
XCZU3	PS_MIO44	J20	MIO44	T25
XCZU3	PS_MIO45	K20	MIO45	T27
XCZU3	PS_MIO46	L20	MIO46	T26
XCZU3	PS_MIO47	H21	MIO47	U26
XCZU3	PS_MIO48	J21	MIO48	T28
XCZU3	PS_MIO49	M18	MIO49	U28
XCZU3	PS_MIO5	AD16	MIO5	W23
XCZU3	PS_MIO50	M19	MIO50	U29
XCZU3	PS_MIO51	L21	MIO51	U27
XCZU3	PS_MIO52	G18	MIO52	P25
XCZU3	PS_MIO53	D16	MIO53	F20
XCZU3	PS_MIO54	F17	MIO54	F21
XCZU3	PS_MIO55	B16	MIO55	E20
XCZU3	PS_MIO56	C16	MIO56	F19
XCZU3	PS_MIO57	A16	MIO57	D20
XCZU3	PS_MIO58	F18	MIO58	L25
XCZU3	PS_MIO59	E17	MIO59	E21
XCZU3	PS_MIO6	AF16	MIO6	V21
XCZU3	PS_MIO60	C17	MIO60	E22
XCZU3	PS_MIO61	D17	MIO61	F22
XCZU3	PS_MIO62	A17	MIO62	D23
XCZU3	PS_MIO63	E18	MIO63	F23
XCZU3	PS_MIO64	E19	MIO64	F24
XCZU3	PS_MIO65	A18	MIO65	A24
XCZU3	PS_MIO66	G19	MIO66	R25
XCZU3	PS_MIO67	B18	MIO67	B24
XCZU3	PS_MIO68	C18	MIO68	D24
XCZU3	PS_MIO69	D19	MIO69	E23
XCZU3	PS_MIO7	AH17	MIO7	W22
XCZU3	PS_MIO70	C19	MIO70	C24
XCZU3	PS_MIO71	B19	MIO71	C25
XCZU3	PS_MIO72	G20	MIO72	P26
XCZU3	PS_MIO73	G21	MIO73	R26
XCZU3	PS_MIO74	D20	MIO74	E24
XCZU3	PS_MIO75	A19	MIO75	A25
XCZU3	PS_MIO76	B20	MIO76	E25
XCZU3	PS_MIO77	F20	MIO77	N25
XCZU3	PS_MIO8	AF17	MIO8	V22
XCZU3	PS_MIO9	AC16	MIO9	V23
XCZU3	PS_MODE0	P19	PS_MODE0	G23	4-bit boot mode pins sampled on POR de-assertion
XCZU3	PS_MODE1	P20	PS_MODE1	G24	4-bit boot mode pins sampled on POR de-assertion
XCZU3	PS_MODE2	R20	PS_MODE2	J23	4-bit boot mode pins sampled on POR de-assertion
XCZU3	PS_MODE3	T20	PS_MODE3	J24	4-bit boot mode pins sampled on POR de-assertion
XCZU3	PS_PADI	N17	PS_PADI	D26	Crystal pad input (RTC) 10 Mohm resistor required to be placed between PS_PADI and PS_PADO to use the RTC
XCZU3	PS_PADO	N18	PS_PADO	F26	Crystal pad input (RTC) 10 Mohm resistor required to be placed between PS_PADI and PS_PADO to use the RTC
XCZU3	PS_POR_B	P16	PS_POR_B	P30	Power-on reset signal (connected internally to PGOOD)
XCZU3	PS_PROG_B	R17	PS_PROG_B	P28	PS configuration reset signal
XCZU3	PS_REF_CLK	R16	PS_REF_CLK	B26	System reference clock connected to the output of internal 33MHz oscillator
XCZU3	PS_SRST_B	N19	PS_SRST_B	T29	System reset commonly used during debug
XCZU3	PUDC_B	U7	PUDC_B	H22	Active low input to enable internal pull-ups during configuration on all SelectIO pins. Pin pulled to VCCAUX to disable Weak preconfiguration I/O pull-up resistors
XCZU3	RSVDGND	U21	VSS	(1)
XCZU3	RSVDGND	V20	VSS	(1)
XCZU3	RSVDGND	V21	VSS	(1)
XCZU3	RSVDGND	W21	VSS	(1)
XCZU3	RSVDGND	Y21	VSS	(1)
XCZU3	VCC_PSADC	Y20	VCC_PSADC	Y29	PS SYSMON ADC supply voltage
XCZU3	VCC_PSAUX	U19	VCC_PSAUX	H24, N23	Powered by PMIC2 VOUT_A
XCZU3	VCC_PSAUX	U20	VCC_PSAUX	H24, N23	Powered by PMIC2 VOUT_A
XCZU3	VCC_PSAUX	V19	VCC_PSAUX	H24, N23	Powered by PMIC2 VOUT_A
XCZU3	VCC_PSAUX	W19	VCC_PSAUX	H24, N23	Powered by PMIC2 VOUT_A
XCZU3	VCC_PSBATT	Y18	VCC_PSBATT	A18	Battery Input
XCZU3	VCC_PSDDR_PLL	U16	VCC_PSDDR_PLL	B18	Need to be Connected externally. See Schematic checklist
XCZU3	VCC_PSDDR_PLL	U18	VCC_PSDDR_PLL	B18	Need to be Connected externally. See Schematic checklist
XCZU3	VCC_PSINTFP	AA15	VCC_PSINTFP	J19, K19	Powered by PMIC2 VOUT_D
XCZU3	VCC_PSINTFP	AA16	VCC_PSINTFP	J19, K19	Powered by PMIC2 VOUT_D
XCZU3	VCC_PSINTFP	AA17	VCC_PSINTFP	J19, K19	Powered by PMIC2 VOUT_D
XCZU3	VCC_PSINTFP	AA18	VCC_PSINTFP	J19, K19	Powered by PMIC2 VOUT_D
XCZU3	VCC_PSINTFP	AB16	VCC_PSINTFP	J19, K19	Powered by PMIC2 VOUT_D
XCZU3	VCC_PSINTFP	Y15	VCC_PSINTFP	J19, K19	Powered by PMIC2 VOUT_D
XCZU3	VCC_PSINTFP	Y17	VCC_PSINTFP	J19, K19	Powered by PMIC2 VOUT_D
XCZU3	VCC_PSINTFP_DDR	AA20	VCC_PSINTFP	J19, K19	Powered by PMIC2 VOUT_D
XCZU3	VCC_PSINTFP_DDR	AA21	VCC_PSINTFP	J19, K19	Powered by PMIC2 VOUT_D
XCZU3	VCC_PSINTFP_DDR	Y19	VCC_PSINTFP	J19, K19	Powered by PMIC2 VOUT_D
XCZU3	VCC_PSINTLP	V16	VCC_PSINTLP	L13, M13	Powered by PMIC2 VOUT_B
XCZU3	VCC_PSINTLP	V17	VCC_PSINTLP	L13, M13	Powered by PMIC2 VOUT_B
XCZU3	VCC_PSINTLP	V18	VCC_PSINTLP	L13, M13	Powered by PMIC2 VOUT_B
XCZU3	VCC_PSINTLP	W15	VCC_PSINTLP	L13, M13	Powered by PMIC2 VOUT_B
XCZU3	VCC_PSINTLP	W16	VCC_PSINTLP	L13, M13	Powered by PMIC2 VOUT_B
XCZU3	VCC_PSINTLP	W17	VCC_PSINTLP	L13, M13	Powered by PMIC2 VOUT_B
XCZU3	VCC_PSPLL	T16	VCC_PSPLL	L17	Powered by PMIC2 VO_LDO
XCZU3	VCC_PSPLL	T17	VCC_PSPLL	L17	Powered by PMIC2 VO_LDO
XCZU3	VCC_PSPLL	T18	VCC_PSPLL	L17	Powered by PMIC2 VO_LDO
XCZU3	VCCADC	P12	VCCADC	A20, B20, B21, C20, D21	PL System Monitor supply
XCZU3	VCCAUX	M16	VCCAUX	G22, P19	Powered by PMIC1 VOUT_A
XCZU3	VCCAUX	N16	VCCAUX	G22, P19	Powered by PMIC1 VOUT_A
XCZU3	VCCAUX_IO	M13	VCCAUX	G22, P19	Powered by PMIC1 VOUT_A
XCZU3	VCCAUX_IO	M14	VCCAUX	G22, P19	Powered by PMIC1 VOUT_A
XCZU3	VCCAUX_IO	M15	VCCAUX	G22, P19	Powered by PMIC1 VOUT_A
XCZU3	VCCBRAM	L11	VCCINT	L11, M11	Powered by PMIC1 VOUT_D
XCZU3	VCCBRAM	L12	VCCINT	L11, M11	Powered by PMIC1 VOUT_D
XCZU3	VCCBRAM	M11	VCCINT	L11, M11	Powered by PMIC1 VOUT_D
XCZU3	VCCBRAM	M12	VCCINT	L11, M11	Powered by PMIC1 VOUT_D
XCZU3	VCCINT	N11	VCCINT	L11, M11	Powered by PMIC1 VOUT_D
XCZU3	VCCINT	N13	VCCINT	L11, M11	Powered by PMIC1 VOUT_D
XCZU3	VCCINT	N15	VCCINT	L11, M11	Powered by PMIC1 VOUT_D
XCZU3	VCCINT	P10	VCCINT	L11, M11	Powered by PMIC1 VOUT_D
XCZU3	VCCINT	P14	VCCINT	L11, M11	Powered by PMIC1 VOUT_D
XCZU3	VCCINT	P15	VCCINT	L11, M11	Powered by PMIC1 VOUT_D
XCZU3	VCCINT	R10	VCCINT	L11, M11	Powered by PMIC1 VOUT_D
XCZU3	VCCINT	R11	VCCINT	L11, M11	Powered by PMIC1 VOUT_D
XCZU3	VCCINT	R14	VCCINT	L11, M11	Powered by PMIC1 VOUT_D
XCZU3	VCCINT	T11	VCCINT	L11, M11	Powered by PMIC1 VOUT_D
XCZU3	VCCINT	T15	VCCINT	L11, M11	Powered by PMIC1 VOUT_D
XCZU3	VCCINT	U10	VCCINT	L11, M11	Powered by PMIC1 VOUT_D
XCZU3	VCCINT	U14	VCCINT	L11, M11	Powered by PMIC1 VOUT_D
XCZU3	VCCINT	U15	VCCINT	L11, M11	Powered by PMIC1 VOUT_D
XCZU3	VCCINT	V10	VCCINT	L11, M11	Powered by PMIC1 VOUT_D
XCZU3	VCCINT	V11	VCCINT	L11, M11	Powered by PMIC1 VOUT_D
XCZU3	VCCINT	V12	VCCINT	L11, M11	Powered by PMIC1 VOUT_D
XCZU3	VCCINT	V14	VCCINT	L11, M11	Powered by PMIC1 VOUT_D
XCZU3	VCCINT_IO	K10	VCCINT	L11, M11	Powered by PMIC1 VOUT_D
XCZU3	VCCINT_IO	L10	VCCINT	L11, M11	Powered by PMIC1 VOUT_D
XCZU3	VCCINT_IO	M10	VCCINT	L11, M11	Powered by PMIC1 VOUT_D
XCZU3	VCCINT_IO	M9	VCCINT	L11, M11	Powered by PMIC1 VOUT_D
XCZU3	VCCO_24	AA14	VCCO_HDIO_24	P20	Need to be Connected externally. See Schematic checklist
XCZU3	VCCO_24	AD13	VCCO_HDIO_24	P20	Need to be Connected externally. See Schematic checklist
XCZU3	VCCO_25	B12	VCCO_HDIO_25	G20	Need to be Connected externally. See Schematic checklist
XCZU3	VCCO_25	E11	VCCO_HDIO_25	G20	Need to be Connected externally. See Schematic checklist
XCZU3	VCCO_26	C15	VCCO_HDIO_26	G21	Need to be Connected externally. See Schematic checklist
XCZU3	VCCO_26	F14	VCCO_HDIO_26	G21	Need to be Connected externally. See Schematic checklist
XCZU3	VCCO_44	AC10	VCCO_HDIO_44	P18	Need to be Connected externally. See Schematic checklist
XCZU3	VCCO_44	AG12	VCCO_HDIO_44	P18	Need to be Connected externally. See Schematic checklist
XCZU3	VCCO_64	AC5	VCCO_HPIO_64	P14	Need to be Connected externally. See Schematic checklist
XCZU3	VCCO_64	AD8	VCCO_HPIO_64	P14	Need to be Connected externally. See Schematic checklist
XCZU3	VCCO_64	AG7	VCCO_HPIO_64	P14	Need to be Connected externally. See Schematic checklist
XCZU3	VCCO_65	H5	VCCO_HPIO_65	G15	Need to be Connected externally. See Schematic checklist
XCZU3	VCCO_65	J3	VCCO_HPIO_65	G15	Need to be Connected externally. See Schematic checklist
XCZU3	VCCO_65	L4	VCCO_HPIO_65	G15	Need to be Connected externally. See Schematic checklist
XCZU3	VCCO_66	B7	VCCO_HPIO_66	G16	Need to be Connected externally. See Schematic checklist
XCZU3	VCCO_66	D3	VCCO_HPIO_66	G16	Need to be Connected externally. See Schematic checklist
XCZU3	VCCO_66	E6	VCCO_HPIO_66	G16	Need to be Connected externally. See Schematic checklist
XCZU3	VCCO_PSDDR_504	AB22	VCCO_PSDDR	L21	Powered by PMIC1 VOUT_C. Only used as a test point
XCZU3	VCCO_PSDDR_504	AD23	VCCO_PSDDR	L21	Powered by PMIC1 VOUT_C. Only used as a test point
XCZU3	VCCO_PSDDR_504	AF24	VCCO_PSDDR	L21	Powered by PMIC1 VOUT_C. Only used as a test point
XCZU3	VCCO_PSDDR_504	P23	VCCO_PSDDR	L21	Powered by PMIC1 VOUT_C. Only used as a test point
XCZU3	VCCO_PSDDR_504	T24	VCCO_PSDDR	L21	Powered by PMIC1 VOUT_C. Only used as a test point
XCZU3	VCCO_PSDDR_504	V25	VCCO_PSDDR	L21	Powered by PMIC1 VOUT_C. Only used as a test point
XCZU3	VCCO_PSDDR_504	Y26	VCCO_PSDDR	L21	Powered by PMIC1 VOUT_C. Only used as a test point
XCZU3	VCCO_PSIO0_500	AB17	VCCO_PSIO_500	P23	Need to be Connected externally. Should be connected to either 1.8V or 3.3V depending on the version of the device. See Schematic checklist.
XCZU3	VCCO_PSIO0_500	AE16	VCCO_PSIO_500	P23	Need to be Connected externally. Should be connected to either 1.8V or 3.3V depending on the version of the device. See Schematic checklist.
XCZU3	VCCO_PSIO0_500	AG17	VCCO_PSIO_500	P23	Need to be Connected externally. Should be connected to either 1.8V or 3.3V depending on the version of the device. See Schematic checklist.
XCZU3	VCCO_PSIO1_501	H20	VCCO_PSIO_501	J25	Need to be Connected externally. See Schematic Checklist
XCZU3	VCCO_PSIO1_501	L19	VCCO_PSIO_501	J25	Need to be Connected externally. See Schematic Checklist
XCZU3	VCCO_PSIO2_502	D18	VCCO_PSIO_502	G25	Need to be Connected externally. See Schematic Checklist
XCZU3	VCCO_PSIO2_502	G17	VCCO_PSIO_502	G25	Need to be Connected externally. See Schematic Checklist
XCZU3	VCCO_PSIO3_503	M17	VCCO_PSIO_503	H23	Need to be Connected externally. See Schematic Checklist
XCZU3	VCCO_PSIO3_503	P18	VCCO_PSIO_503	H23	Need to be Connected externally. See Schematic Checklist
XCZU3	VN	T12	VN	A22	System Monitor dedicated differential analog input. Should be tied to GNDADC if unused
XCZU3	VP	R13	VP	A21	System Monitor dedicated differential analog input. Should be tied to GNDADC if unused
XCZU3	VREF_64	AA7	VREF_64	N14	Need to be Connected externally. See Schematic Checklist
XCZU3	VREF_65	R9	VREF_65	H15	Need to be Connected externally. See Schematic Checklist
XCZU3	VREF_66	G9	VREF_66	H16	Need to be Connected externally. See Schematic Checklist
XCZU3	VREFN	R12	VREFN	C22	Voltage reference GND
XCZU3	VREFP	T13	VREFP	C21	Voltage reference input

Notes:

(1)	See VSS pin in OSD32MP15x datasheet.				D4, E10, E11, E12, E13, E14, E15, E4, E5, E6, E7, E8, E9, F10, F11, F12, F13, F14, F15, F4, F5, F6, F7, F8, F9, G11, G12, G13, G14, G15, G5, H13, H14, H15, H5, J13, J14, J15, J16, J5, K13, K14, K15, K16, K5, L13, L14, L15, L5, M11, M12, M13, M14, M15, M5, N10, N11, N12, N13, N14, N15, N5, N6, N7, N8, N9, P5, P6, P7, P8
(2)	See RSVD pin in OSDZU3 datasheet.				A11, E3, L19, M16, M17, M21, M22, N18, N19, N20, P16, P17, P21, P22, W27, Y27

Revision History

Revision Number	Revision Date	Changes	Author
1	11/27/2023	Initial Version	Erik Welsh

Notice

The information provided within this document is for informational use only. Octavo Systems provides no guarantees or warranty to the information contained.

Related Products

Pin Mapping between OSDZU3 and the XCZU3

OSDZU3 to Discrete Mapping

Notes:

Discrete to OSDZU3 Mapping

Notes:

Revision History