RMII2_Ref_Clk

This topic has 5 replies, 2 voices, and was last updated 2 years, 2 months ago by VHPonline.

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- September 6, 2022 at 10:33 am #12635
  VHPonline
  Participant
  Hello,
  
  I cannot seem to find the pin where to connect the RMII2_Ref_Clk for the 2nd ethernet PHY.
  Does anyone know where to find it?
  
  Thanks!
  
  Best regards,
  Ronald
- September 7, 2022 at 6:41 am #12637
  VHPonline
  Participant
  It seems that it does not have a reference clock for the 2nd PHY.
  Do I need to synchronize both PHYs to each other?
- September 8, 2022 at 10:33 am #12641
  Aedan Cullen
  Participant
  There is indeed an RMII2 reference clock signal, but it’s just not on a pin named RMII2_REF_CLK. Instead, it’s one of the alternate signals available for the pin MII1_COL. That’s the pin you’ll want to use.
  (If you search the AM335x datasheet for “rmii2_refclk”, you can see that this signal appears on ball H16 of the ZCZ package, which corresponds to ball F15 on the OSD335x-SM. In Octavo’s schematic symbol for the OSD335x-SM, the pin name is kept as MII1_COL.)
  For an example of this usage, you can take a look at TI’s AM335x ICE V2 board, which has two PHYs over RMII. In its devicetree, AM335X_PIN_MII1_COL is set to MUX_MODE1 to use it as the “rmii2_refclk” input.
- September 8, 2022 at 11:07 am #12642
  VHPonline
  Participant
  Thank you so much! Just the info I was looking for.
  would you also have a link to the AM335x ICE V2 board schematics? If I search for them through Google I only get the schematics for the V1 board, which seems to use MII instead of RMII.
- September 8, 2022 at 12:08 pm #12643
  Aedan Cullen
  Participant
  This forum isn’t letting me post links, probably to filter spam. The schematic for V2.1 is in an archive called “tidr336.zip” which you can find if you put that into the search box on the TI website. It actually has the PHYs connected both to the PRUs and to the CPSW (the main ethernet switch that you use from the Cortex-A8) so there’s some extra mux stuff on sheet 10 which you likely may not need for your application. I haven’t yet familiarized myself with the configuration of the PRUs here, and it seems that MII is used in that case. But with Linux, RMII is definitely being used – if you Google am335x-icev2.dts and go to line 202, you can see the CPSW pin configuration with RXD0, RXD1, TXD0, TXD1, and the refclk pins.
- September 9, 2022 at 6:30 am #12644
  VHPonline
  Participant
  Quite a puzzle, but we are getting there.
  So it appears that I did actually have the correct schematics. The thing is that the PHYs are wired for MII at the PHY side, but the wiring at the AM335x also mention the RMII signal names. So it looks like it can run in both RMII and MII modes. The fact that you saw that the device tree is configured for RMII is a great help to me. That proves that the wiring is actually RMII compatible.
  
  So thanks again!
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