Ethernet not working

This topic has 2 replies, 1 voice, and was last updated 2 years, 8 months ago by BillR.

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- March 9, 2022 at 1:57 pm #12125
  BillR
  Participant
  We have a board based on the Redboard, but using a KSZ9021GN PHY in MII 100mbit mode, but I have no direct example of using this specific part.
  I have modified device tree(s) to accommodate it, using other references such as Cube MX generation, Redboard (but which uses a RGMII phy).
  The part is seen OK
  [ 3.034691] stm32-dwmac 5800a000.ethernet: PTP uses main clock
  [ 3.039075] stm32-dwmac 5800a000.ethernet: no reset control found
  [ 3.045313] stm32-dwmac 5800a000.ethernet: No phy clock provided…
  [ 3.052115] stm32-dwmac 5800a000.ethernet: User ID: 0x40, Synopsys ID: 0x42
  [ 3.058386] stm32-dwmac 5800a000.ethernet: DWMAC4/5
  [ 3.063393] stm32-dwmac 5800a000.ethernet: DMA HW capability register supported
  [ 3.070688] stm32-dwmac 5800a000.ethernet: RX Checksum Offload Engine supported
  [ 3.077952] stm32-dwmac 5800a000.ethernet: TX Checksum insertion supported
  [ 3.084849] stm32-dwmac 5800a000.ethernet: Wake-Up On Lan supported
  [ 3.091109] stm32-dwmac 5800a000.ethernet: TSO supported
  [ 3.096395] stm32-dwmac 5800a000.ethernet: Enable RX Mitigation via HW Watchdog Timer
  [ 3.104264] stm32-dwmac 5800a000.ethernet: device MAC address 2a:b6:bd:41:64:49
  [ 3.111559] stm32-dwmac 5800a000.ethernet: TSO feature enabled
  But then when started, has the familiar issue of:
  [ 15.650981] dwmac4_dma_reset err
  [ 15.652849] stm32-dwmac 5800a000.ethernet: Failed to reset the dma
  [ 15.659006] stm32-dwmac 5800a000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed
  [ 15.668518] stm32-dwmac 5800a000.ethernet eth0: stmmac_open: Hw setup failed
  What are the dependencies of tf-a and u-boot in this working?
  tf-a seems to need to enable the ethernet PLL4P clock. I am concerned that its something to do with not configuring this clock right.
  Thanks.
- March 9, 2022 at 3:22 pm #12126
  BillR
  Participant
  Basic device tree in linux (u-boot same)
  // …
  eth1_pins_mx: eth1_mx-0 {
  pins1 {
  pinmux = <STM32_PINMUX(‘A’, 1, AF11)>, /* ETH1_RX_CLK */
  <STM32_PINMUX(‘A’, 7, AF11)>, /* ETH1_RX_DV */
  <STM32_PINMUX(‘C’, 3, AF11)>, /* ETH1_TX_CLK */
  <STM32_PINMUX(‘C’, 4, AF11)>, /* ETH1_RXD0 */
  <STM32_PINMUX(‘C’, 5, AF11)>, /* ETH1_RXD1 */
  <STM32_PINMUX(‘B’, 0, AF11)>, /* ETH1_RXD2 */
  <STM32_PINMUX(‘B’, 1, AF11)>; /* ETH1_RXD3 */
  bias-disable;
  };
  pins2 {
  pinmux = <STM32_PINMUX(‘A’, 2, AF11)>; /* ETH1_MDIO */
  bias-disable;
  drive-push-pull;
  slew-rate = <0>;
  };
  pins3 {
  pinmux = <STM32_PINMUX(‘B’, 11, AF11)>; /* ETH1_TX_EN */
  };
  pins4 {
  pinmux = <STM32_PINMUX(‘C’, 1, AF11)>, /* ETH1_MDC */
  <STM32_PINMUX(‘C’, 2, AF11)>, /* ETH1_TXD2 */
  <STM32_PINMUX(‘E’, 2, AF11)>, /* ETH1_TXD3 */
  <STM32_PINMUX(‘G’, 13, AF11)>, /* ETH1_TXD0 */
  <STM32_PINMUX(‘G’, 14, AF11)>; /* ETH1_TXD1 */
  bias-disable;
  drive-push-pull;
  slew-rate = <1>;
  };
  };
  eth1_sleep_pins_mx: eth1_sleep_mx-0 {
  pins {
  pinmux = <STM32_PINMUX(‘A’, 1, ANALOG)>, /* ETH1_RX_CLK */
  <STM32_PINMUX(‘A’, 7, ANALOG)>, /* ETH1_RX_DV */
  <STM32_PINMUX(‘A’, 2, ANALOG)>, /* ETH1_MDIO */
  <STM32_PINMUX(‘C’, 1, ANALOG)>, /* ETH1_MDC */
  <STM32_PINMUX(‘B’, 11, ANALOG)>,/* ETH1_TX_EN */
  <STM32_PINMUX(‘C’, 3, ANALOG)>, /* ETH1_TX_CLK */
  <STM32_PINMUX(‘C’, 4, ANALOG)>, /* ETH1_RXD0 */
  <STM32_PINMUX(‘C’, 5, ANALOG)>, /* ETH1_RXD1 */
  <STM32_PINMUX(‘B’, 0, ANALOG)>, /* ETH1_RXD2 */
  <STM32_PINMUX(‘B’, 1, ANALOG)>, /* ETH1_RXD3 */
  <STM32_PINMUX(‘G’, 13, ANALOG)>,/* ETH1_TXD0 */
  <STM32_PINMUX(‘G’, 14, ANALOG)>,/* ETH1_TXD1 */
  <STM32_PINMUX(‘C’, 2, ANALOG)>, /* ETH1_TXD2 */
  <STM32_PINMUX(‘E’, 2, ANALOG)>; /* ETH1_TXD3 */
  };
  };
  // …
  &ethernet0{
  pinctrl-names = “default”, “sleep”;
  pinctrl-0 = <&eth1_pins_mx>;
  pinctrl-1 = <&eth1_sleep_pins_mx>;
  status = “okay”;
  st,eth_clk_sel = <1>;
  phy-mode = “mii”;
  max-speed = <100>;
  phy-handle = <&phy0>;
  mdio0 {
  #address-cells = <1>;
  #size-cells = <0>;
  compatible = “snps,dwmac-mdio”;
  phy0: ethernet-phy@0 {
  reg = <3>;
  };
  };
  };
- March 10, 2022 at 9:49 am #12131
  BillR
  Participant
  Never mind, our board has a wiring problem.
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