SDMMC and GbE performance versus VDD

hello,

We are designing with the OSD32MP153C-512M-BAA (the prototypes will have OSD32MP157C-512M-IAA).
The VDD voltage in the SiP sets the I/O voltage of the STM32MP15x (in addition to other circuitry) and in particular the I/Os that are used for the eMMC Flash and RGMII interfaces.
I would like to use a VDD of 3.3V.
As far as I understand, this will limit the performance I can get from my eMMC Flash to DDR52, according to “Table 402. SDMMC operation modes e•MMC in RM0442 Reference manual STM32MP153” (attached).
The table states 3V. I guess 3.3V is also fine.
So, for HS200 I will need signaling voltage of 1.8V, thus VDD of 1.8V.
This will affect all the I/Os voltage of the entire SoC GPIOs, JTAG bus voltage, not-activating the VDDA1V8_REG (bypassing it), etc.

Am I correct?
Can anyone comment or add anything on that?

In addition, I want to use the GbE RGMII interface.
Do I require a VDD of 1.8V for that?

If VDD of 1.8V is required, how will that affect the design?
I am aware of bypassing REG1V8 (connect BYPASS_REG1V8 to VDD) and connecting VDD (1.8V) to VDDA1V8_REG pin.
Anything else?

Thank you
Gil

• This topic was modified 2 years, 11 months ago by gil_he.
• This topic was modified 2 years, 11 months ago by gil_he.