OSDZU3 PetaLinux Application Note Part 1: Vivado Hardware Configuration

Introduction

In this application note, we will walk through how to create a basic PetaLinux image for OSDZU3-REF platform. First, we will generate a hardware platform in Vivado based on OSDZU3-REF’s Board Definition File(BDF) that Octavo makes available. The, we will export the hardware file to import it into a new PetaLinux project. We will then configure PetaLinux to generate a minimal image that we will flash on to an SD card. Finally, we will use the image to boot OSDZU3-REF board.

Then, in Part 2 of the tutorial, we will configure PetaLinux to generate a minimal image that we will flash onto an SD card. Finally, we will use the image to boot the OSDZU3-REF board.

Creating Harware platform

1. Open Vivado version 2024.2

2. Click on Tools→Settings

3. Select Tool Settings → Vivado Store → Board Repository

4. Click on the + button to add the location of the board definition file to Vivado’s repository list

Browse to the location of the board definition files for OSDZU3-REF and click select at the bottom of the Select box

The Board Repository section should look like this:

The above image shows OSDZU3-REF and OSDZU3-2G-xFB board definition files setup in the board repository for the Vivado project. You can use either one of these board definition files.

Click OK at the bottom of the screen to close to the Settings window

Creating a new Vivado Project

1. Click on Create Project at the top of the Quick Start menu

2. Name the project in Project name section and set the location of the project at your preferred location in the file system in the Project location section

Click on Next

3. Select RTL Project and keep “Do not specify sources at the time” option ticked:

Click on Next

4. In Default Part selection window, select “Boards” at the top of the window. Octavo OSDZU3 Reference Design should appear as an option:

Select “Octavo OSDZU3 Reference Design” and click Next

5. A summary of the project configuration should be displayed like shown below:

Click on Finish

6. Here is what Vivado looks like after you initialized the project:

7. Click on Create Block Design in IP Integrator section of the Project Manager:

8. Add a Design Name and click OK on the Create Block Design dialog box:

9. You will see a new Diagram window pop-up. Click on + button in the middle of the window to add IP to your block diagram:

10. Search for zynq core in searchbox and double click on it to add it to the block diagram

11. You will see the following in the block diagram window:

12. Click on Run Block Automation. Vivado will ask you if you want to apply the board preset to zynq_ulta_ps_e_0. Make sure the box for this IP is ticked as well as the box for “Apply Board Preset” option. Click on OK.

This will apply all the configuration defined in the Board Definition File based on which the platform was created.

13. Double click on zynq_ulta_ps_e_0 to make other changes to the PS(Processing System) subsystem, PS-PL (Programmable Logic) interface as well as the clocking architecture for your design. The following Re-customize IP window will appear:

You can click on any of the boxes or browse to different sections of the configuration such as I/O Configuration, Clock Configuration etc.

14. I/O configuration options are shown below:

15. Clock configuration options in the Clock Configuration tab are shown below:

16. You can change the pinmux/clock settings for each peripheral. For example, configuration of GTR lanes for different use cases can be configured in the IO configuration tab in “High Speed” section as shown below:

17. After configuration, click on OK. Click on Validate design option in the Block Diagram window to let Vivado check if there are any errors on configuration. You will see something like the following if there are issues:

Some examples of issues the validation process will catch:

– Clock sources (PL clocks vs PS clocks)

– Reset sources and polarity

– MIO/EMIO pin usage conflicts

– PS configuration legality (e.g. can’t enable both SD0 on MIO and QSPI on overlapping pins)

– Unused ports incorrectly left floating

– Parameter mismatches between PS and IP connected to it (like AXI clock frequencies)

18. Here in the above case, maxihpm0_lpd_aclk is the AXI clock input for the PS’s M_AXI_HPM0_LPD master port (the Low-Power-Domain HPM port). When you enable that PS master interface, Vivado expects you to feed it a real clock (a net driven by a recognized “clock source” pin). To resolve this, PL fabric clock and and PL Fabric Reset Enable are configured in the PS block. All you have to do is to route the pl_clk0 to the maxihpm0_lpd_aclk. Here is the block diagram with clock connection made:

With this connection added, validation should be successful.

19. Once validation is successful and all configuration is done, click on Sources → Designs Sources, then Right click on the block diagram you created (osdzu3_ref_hw) and click on Create HDL Wrapper.

20. Chose the option to let Vivado manage wrapper and auto-update:

There are additional steps to create a hardware platform if more blocks are added. Any external pins must need Constraints and pin configuration. For the scope of this app note, we are considering basic PS setup and Petalinux. Please refer to “Vivado tutorial(https://octavosystems.com/app_notes/osdzu3-vivado-tutorial/)” for additional information on PL configuration.

21. For this app note, we are ready to generate bitstream for our hardware platform. Click on Program and Debug → Generate Bitstream:

22. Set the Number of jobs based on the CPU core count of your machine and click OK:

23. Once finished, Vivado will show the following options:

24. The final step in Vivado is to export the hardware platform for Vitis/PetaLinux. For this, click on File→Export→Export Hardware

25. The exporting wizard will pop up. Click on Next

26. Select Output option : Include bitstream and click on Next.

27. Add name of the .XSA file and Export to location and click on Next

28. Click on Finish to start the export:

Part 2 here: https://octavosystems.com/app_notes/osdzu3-petalinux-application-note-part-2-2024-2/

Revision Number	Revision Date	Changes	Author
1	03/03/2026	Added revision history section and formatted document per review comments	Neeraj Dantu
2	03/03/2026	Updated introduction to reference Part 2, numbered all steps	Neeraj Dantu

OSDZU3 PetaLinux Application Note Part 1: Vivado Hardware Configuration

Introduction

Creating Harware platform

Creating a new Vivado Project

Table of Contents

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OSDZU3 PetaLinux Application Note Part 1: Vivado Hardware Configuration

Introduction

Creating Harware platform

Creating a new Vivado Project

Table of Contents

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