Pin Mapping Between OSD62x-PM and the AM62x

Published On: June, 5, 2025 By: erikwelsh | Updated: June 26, 2025 by Greg Sheridan

This document is a quick reference to understand the mapping of the pins between the OSD62x-PM Family of devices, the AM6254 processor AMC package and other devices contained within.

This application note contains two tables:
1. Mapping sorted by OSD62x-PM Signal Name
2. Mapping sorted by Discrete Device and Signal Names

There are a couple of high level differences between the OSD62x-PM and the AM6254 processor AMC package that are helpful to understand when using this document:

The OSD62x-PM integrates the DDR. Therefore all DDR related pins are not pinned out on the AM6254.
The OSD62x-PM does not integrate the power management IC (PMIC). However, it does integrate some of the power management passives.

An Excel Workbook containing these tables and others can be downloaded here.

These tables have multiple pages. Each column can be sorted using the arrows in the column header. they can be searched by using the respective search box.

OSD62x-PM to AM6254 Pin Mapping

OSD62x-PM Pin Name	OSD62x-PM Pin Number	Discrete Device	Discrete Device Signal Name	Discrete Device Pin Number (AMC Package)	Comments
AM62X_RSVD0	F5	AM6254	RSVD0	B3	Reserved Pin
AM62X_RSVD1	F4	AM6254	RSVD1	C3	Reserved Pin
AM62X_RSVD2	F6	AM6254	RSVD2	E6	Reserved Pin
AM62X_RSVD3	N17	AM6254	RSVD3	F8	Reserved Pin
AM62X_RSVD4	F8	AM6254	RSVD4	R6	Reserved Pin
AM62X_RSVD5	F9	AM6254	RSVD5	T13	Reserved Pin
AM62X_RSVD6	M18	AM6254	RSVD6	T14	Reserved Pin
AM62X_RSVD7	N18	AM6254	RSVD7	M4	Reserved Pin
AM62X_RSVD8	F7	AM6254	RSVD8	M5	Reserved Pin
CSI0_RXCLKN	V17	AM6254	CSI0_RXCLKN	AA14
CSI0_RXCLKP	U17	AM6254	CSI0_RXCLKP	AA13
CSI0_RXN0	V16	AM6254	CSI0_RXN0	Y13
CSI0_RXN1	V15	AM6254	CSI0_RXN1	V13
CSI0_RXN2	U14	AM6254	CSI0_RXN2	U12
CSI0_RXN3	U13	AM6254	CSI0_RXN3	W12
CSI0_RXP0	U16	AM6254	CSI0_RXP0	Y12
CSI0_RXP1	U15	AM6254	CSI0_RXP1	V12
CSI0_RXP2	V14	AM6254	CSI0_RXP2	U11
CSI0_RXP3	V13	AM6254	CSI0_RXP3	W11
DDR_RSVD0	F10	DDR	NA	NA	Reserved Pin
DDR_VPP	N10	DDR	NA	NA
EMU0	D8	AM6254	EMU0	D9
EMU1	C8	AM6254	EMU1	B10
EXT_REFCLK1	D16	AM6254	EXT_REFCLK1	C14
EXTINTN	C17	AM6254	EXTINTN	B16
GPMC0_AD0	G28	AM6254	GPMC0_AD0	K19
GPMC0_AD1	G27	AM6254	GPMC0_AD1	L19
GPMC0_AD10	K27	AM6254	GPMC0_AD10	M17
GPMC0_AD11	K28	AM6254	GPMC0_AD11	N18
GPMC0_AD12	J28	AM6254	GPMC0_AD12	N17
GPMC0_AD13	J27	AM6254	GPMC0_AD13	N19
GPMC0_AD14	H28	AM6254	GPMC0_AD14	P19
GPMC0_AD15	H27	AM6254	GPMC0_AD15	P20
GPMC0_AD2	F28	AM6254	GPMC0_AD2	L20
GPMC0_AD3	F27	AM6254	GPMC0_AD3	L21
GPMC0_AD4	E28	AM6254	GPMC0_AD4	M21
GPMC0_AD5	E27	AM6254	GPMC0_AD5	L17
GPMC0_AD6	D28	AM6254	GPMC0_AD6	L18
GPMC0_AD7	D27	AM6254	GPMC0_AD7	M20
GPMC0_AD8	L27	AM6254	GPMC0_AD8	N20
GPMC0_AD9	L28	AM6254	GPMC0_AD9	N21
GPMC0_ADVN_ALE	H25	AM6254	GPMC0_ADVN_ALE	K20
GPMC0_BE0N_CLE	J26	AM6254	GPMC0_BE0N_CLE	K17
GPMC0_BE1N	K25	AM6254	GPMC0_BE1N	K18
GPMC0_CLK	K26	AM6254	GPMC0_CLK	M19
GPMC0_CSN0	F26	AM6254	GPMC0_CSN0	J18
GPMC0_CSN1	F25	AM6254	GPMC0_CSN1	H17
GPMC0_CSN2	E26	AM6254	GPMC0_CSN2	H18
GPMC0_CSN3	E25	AM6254	GPMC0_CSN3	H19
GPMC0_DIR	G25	AM6254	GPMC0_DIR	J19
GPMC0_OEN_REN	H26	AM6254	GPMC0_OEN_REN	K21
GPMC0_WAIT0	L25	AM6254	GPMC0_WAIT0	P21
GPMC0_WAIT1	L26	AM6254	GPMC0_WAIT1	P17
GPMC0_WEN	J25	AM6254	GPMC0_WEN	J17
GPMC0_WPN	G26	AM6254	GPMC0_WPN	J20
I2C0_SCL	A12	AM6254	I2C0_SCL	E12
I2C0_SDA	B12	AM6254	I2C0_SDA	D14
I2C1_SCL	A13	AM6254	I2C1_SCL	A17
I2C1_SDA	B13	AM6254	I2C1_SDA	A16
MCAN0_RX	A11	AM6254	MCAN0_RX	A15
MCAN0_TX	B11	AM6254	MCAN0_TX	B13
MCASP0_ACLKR	B19	AM6254	MCASP0_ACLKR	D16
MCASP0_ACLKX	A18	AM6254	MCASP0_ACLKX	C17
MCASP0_AFSR	A19	AM6254	MCASP0_AFSR	D15
MCASP0_AFSX	B18	AM6254	MCASP0_AFSX	C16
MCASP0_AXR0	B17	AM6254	MCASP0_AXR0	D18
MCASP0_AXR1	A17	AM6254	MCASP0_AXR1	A18
MCASP0_AXR2	B16	AM6254	MCASP0_AXR2	B17
MCASP0_AXR3	A16	AM6254	MCASP0_AXR3	B18
MCU_ERRORN	D7	AM6254	MCU_ERRORN	B1
MCU_I2C0_SCL	A7	AM6254	MCU_I2C0_SCL	B9
MCU_I2C0_SDA	B7	AM6254	MCU_I2C0_SDA	A10
MCU_MCAN0_RX	E1	AM6254	MCU_MCAN0_RX	C4
MCU_MCAN0_TX	E2	AM6254	MCU_MCAN0_TX	C5
MCU_MCAN1_RX	F1	AM6254	MCU_MCAN1_RX	D6
MCU_MCAN1_TX	F2	AM6254	MCU_MCAN1_TX	D5
MCU_OSC0_XI	G1	AM6254	MCU_OSC0_XI	A5
MCU_OSC0_XO	G2	AM6254	MCU_OSC0_XO	A6
MCU_PORZ	D6	AM6254	MCU_PORZ	B2
MCU_RESETSTATZ	C6	AM6254	MCU_RESETSTATZ	A12
MCU_RESETZ	C5	AM6254	MCU_RESETZ	C9
MCU_SPI0_CLK	A4	AM6254	MCU_SPI0_CLK	B7
MCU_SPI0_CS0	B6	AM6254	MCU_SPI0_CS0	E7
MCU_SPI0_CS1	A6	AM6254	MCU_SPI0_CS1	C8
MCU_SPI0_D0	B5	AM6254	MCU_SPI0_D0	E8
MCU_SPI0_D1	A5	AM6254	MCU_SPI0_D1	D8
MCU_UART0_CTSN	B4	AM6254	MCU_UART0_CTSN	B8
MCU_UART0_RTSN	A3	AM6254	MCU_UART0_RTSN	D7
MCU_UART0_RXD	B2	AM6254	MCU_UART0_RXD	A8
MCU_UART0_TXD	B3	AM6254	MCU_UART0_TXD	B6
MDIO0_MDC	V26	AM6254	MDIO0_MDC	V17
MDIO0_MDIO	U26	AM6254	MDIO0_MDIO	U16
MMC0_CLK	J1	AM6254	MMC0_CLK	Y1
MMC0_CMD	K1	AM6254	MMC0_CMD	V3
MMC0_DAT0	K2	AM6254	MMC0_DAT0	V2
MMC0_DAT1	L1	AM6254	MMC0_DAT1	V1
MMC0_DAT2	L2	AM6254	MMC0_DAT2	W2
MMC0_DAT3	M1	AM6254	MMC0_DAT3	W1
MMC0_DAT4	M2	AM6254	MMC0_DAT4	Y2
MMC0_DAT5	N1	AM6254	MMC0_DAT5	W3
MMC0_DAT6	N2	AM6254	MMC0_DAT6	W4
MMC0_DAT7	P1	AM6254	MMC0_DAT7	V4
MMC1_CLK	B21	AM6254	MMC1_CLK	A20
MMC1_CMD	A21	AM6254	MMC1_CMD	C18
MMC1_DAT0	A22	AM6254	MMC1_DAT0	A19
MMC1_DAT1	B22	AM6254	MMC1_DAT1	B19
MMC1_DAT2	A20	AM6254	MMC1_DAT2	B20
MMC1_DAT3	B20	AM6254	MMC1_DAT3	C19
MMC1_SDCD	A23	AM6254	MMC1_SDCD	C15
MMC1_SDWP	B23	AM6254	MMC1_SDWP	B15
MMC2_CLK	D23	AM6254	MMC2_CLK	E21
MMC2_CMD	C23	AM6254	MMC2_CMD	C21
MMC2_DAT0	D22	AM6254	MMC2_DAT0	B21
MMC2_DAT1	C22	AM6254	MMC2_DAT1	D21
MMC2_DAT2	D21	AM6254	MMC2_DAT2	E19
MMC2_DAT3	C21	AM6254	MMC2_DAT3	E20
MMC2_SDCD	D20	AM6254	MMC2_SDCD	D20
MMC2_SDWP	C20	AM6254	MMC2_SDWP	C20
NC	E14	AM6254	NC	See Note (2)	Do not connect or route through
NC	E15	AM6254	NC	See Note (2)	Do not connect or route through
NC	F3	AM6254	NC	See Note (2)	Do not connect or route through
NC	F15	AM6254	NC	See Note (2)	Do not connect or route through
NC	F16	AM6254	NC	See Note (2)	Do not connect or route through
NC	F17	AM6254	NC	See Note (2)	Do not connect or route through
NC	F18	AM6254	NC	See Note (2)	Do not connect or route through
NC	G3	AM6254	NC	See Note (2)	Do not connect or route through
NC	G4	AM6254	NC	See Note (2)	Do not connect or route through
NC	G5	AM6254	NC	See Note (2)	Do not connect or route through
NC	G6	AM6254	NC	See Note (2)	Do not connect or route through
NC	G7	AM6254	NC	See Note (2)	Do not connect or route through
NC	G8	AM6254	NC	See Note (2)	Do not connect or route through
NC	G9	AM6254	NC	See Note (2)	Do not connect or route through
NC	G17	AM6254	NC	See Note (2)	Do not connect or route through
NC	G18	AM6254	NC	See Note (2)	Do not connect or route through
NC	H3	AM6254	NC	See Note (2)	Do not connect or route through
NC	H4	AM6254	NC	See Note (2)	Do not connect or route through
NC	H5	AM6254	NC	See Note (2)	Do not connect or route through
NC	H6	AM6254	NC	See Note (2)	Do not connect or route through
NC	H7	AM6254	NC	See Note (2)	Do not connect or route through
NC	H8	AM6254	NC	See Note (2)	Do not connect or route through
NC	H9	AM6254	NC	See Note (2)	Do not connect or route through
NC	H10	AM6254	NC	See Note (2)	Do not connect or route through
NC	H11	AM6254	NC	See Note (2)	Do not connect or route through
NC	H23	AM6254	NC	See Note (2)	Do not connect or route through
NC	J2	AM6254	NC	See Note (2)	Do not connect or route through
NC	J3	AM6254	NC	See Note (2)	Do not connect or route through
NC	J4	AM6254	NC	See Note (2)	Do not connect or route through
NC	J5	AM6254	NC	See Note (2)	Do not connect or route through
NC	J6	AM6254	NC	See Note (2)	Do not connect or route through
NC	J7	AM6254	NC	See Note (2)	Do not connect or route through
NC	J8	AM6254	NC	See Note (2)	Do not connect or route through
NC	J9	AM6254	NC	See Note (2)	Do not connect or route through
NC	J10	AM6254	NC	See Note (2)	Do not connect or route through
NC	J11	AM6254	NC	See Note (2)	Do not connect or route through
NC	J23	AM6254	NC	See Note (2)	Do not connect or route through
NC	K3	AM6254	NC	See Note (2)	Do not connect or route through
NC	K4	AM6254	NC	See Note (2)	Do not connect or route through
NC	K5	AM6254	NC	See Note (2)	Do not connect or route through
NC	K23	AM6254	NC	See Note (2)	Do not connect or route through
NC	L3	AM6254	NC	See Note (2)	Do not connect or route through
NC	L4	AM6254	NC	See Note (2)	Do not connect or route through
NC	L12	AM6254	NC	See Note (2)	Do not connect or route through
NC	L16	AM6254	NC	See Note (2)	Do not connect or route through
NC	L23	AM6254	NC	See Note (2)	Do not connect or route through
NC	M3	AM6254	NC	See Note (2)	Do not connect or route through
NC	M11	AM6254	NC	See Note (2)	Do not connect or route through
NC	M14	AM6254	NC	See Note (2)	Do not connect or route through
NC	M15	AM6254	NC	See Note (2)	Do not connect or route through
NC	M16	AM6254	NC	See Note (2)	Do not connect or route through
NC	M17	AM6254	NC	See Note (2)	Do not connect or route through
NC	M19	AM6254	NC	See Note (2)	Do not connect or route through
NC	N15	AM6254	NC	See Note (2)	Do not connect or route through
NC	N16	AM6254	NC	See Note (2)	Do not connect or route through
NC	N19	AM6254	NC	See Note (2)	Do not connect or route through
NC	P6	AM6254	NC	See Note (2)	Do not connect or route through
NC	P7	AM6254	NC	See Note (2)	Do not connect or route through
NC	P8	AM6254	NC	See Note (2)	Do not connect or route through
NC	P9	AM6254	NC	See Note (2)	Do not connect or route through
NC	P14	AM6254	NC	See Note (2)	Do not connect or route through
NC	P15	AM6254	NC	See Note (2)	Do not connect or route through
NC	R5	AM6254	NC	See Note (2)	Do not connect or route through
NC	R6	AM6254	NC	See Note (2)	Do not connect or route through
NC	R7	AM6254	NC	See Note (2)	Do not connect or route through
NC	R8	AM6254	NC	See Note (2)	Do not connect or route through
NC	R9	AM6254	NC	See Note (2)	Do not connect or route through
NC	R10	AM6254	NC	See Note (2)	Do not connect or route through
NC	R11	AM6254	NC	See Note (2)	Do not connect or route through
NC	R12	AM6254	NC	See Note (2)	Do not connect or route through
NC	R13	AM6254	NC	See Note (2)	Do not connect or route through
NC	R14	AM6254	NC	See Note (2)	Do not connect or route through
NC	R15	AM6254	NC	See Note (2)	Do not connect or route through
NC	R16	AM6254	NC	See Note (2)	Do not connect or route through
NC	R17	AM6254	NC	See Note (2)	Do not connect or route through
NC	R18	AM6254	NC	See Note (2)	Do not connect or route through
NC	T4	AM6254	NC	See Note (2)	Do not connect or route through
NC	T5	AM6254	NC	See Note (2)	Do not connect or route through
NC	T6	AM6254	NC	See Note (2)	Do not connect or route through
NC	T7	AM6254	NC	See Note (2)	Do not connect or route through
NC	T8	AM6254	NC	See Note (2)	Do not connect or route through
NC	T9	AM6254	NC	See Note (2)	Do not connect or route through
NC	T10	AM6254	NC	See Note (2)	Do not connect or route through
NC	T11	AM6254	NC	See Note (2)	Do not connect or route through
NC	T12	AM6254	NC	See Note (2)	Do not connect or route through
NC	T13	AM6254	NC	See Note (2)	Do not connect or route through
NC	T14	AM6254	NC	See Note (2)	Do not connect or route through
NC	T15	AM6254	NC	See Note (2)	Do not connect or route through
NC	T16	AM6254	NC	See Note (2)	Do not connect or route through
NC	T17	AM6254	NC	See Note (2)	Do not connect or route through
NC	T18	AM6254	NC	See Note (2)	Do not connect or route through
NC	U18	AM6254	NC	See Note (2)	Do not connect or route through
NC	V18	AM6254	NC	See Note (2)	Do not connect or route through
OLDI0_A0N	P2	AM6254	OLDI0_A0N	AA2
OLDI0_A0P	R1	AM6254	OLDI0_A0P	AA3
OLDI0_A1N	R2	AM6254	OLDI0_A1N	V5
OLDI0_A1P	T1	AM6254	OLDI0_A1P	V6
OLDI0_A2N	T2	AM6254	OLDI0_A2N	U7
OLDI0_A2P	U2	AM6254	OLDI0_A2P	U6
OLDI0_A3N	U3	AM6254	OLDI0_A3N	W6
OLDI0_A3P	V3	AM6254	OLDI0_A3P	W5
OLDI0_A4N	U4	AM6254	OLDI0_A4N	AA4
OLDI0_A4P	V4	AM6254	OLDI0_A4P	Y5
OLDI0_A5N	U5	AM6254	OLDI0_A5N	AA6
OLDI0_A5P	V5	AM6254	OLDI0_A5P	AA5
OLDI0_A6N	U6	AM6254	OLDI0_A6N	AA10
OLDI0_A6P	V6	AM6254	OLDI0_A6P	Y9
OLDI0_A7N	U7	AM6254	OLDI0_A7N	AA8
OLDI0_A7P	V7	AM6254	OLDI0_A7P	Y8
OLDI0_CLK0N	U8	AM6254	OLDI0_CLK0N	V7
OLDI0_CLK0P	V8	AM6254	OLDI0_CLK0P	V8
OLDI0_CLK1N	U9	AM6254	OLDI0_CLK1N	Y7
OLDI0_CLK1P	V9	AM6254	OLDI0_CLK1P	AA7
OSPI0_CLK	A24	AM6254	OSPI0_CLK	G19
OSPI0_CSN0	D25	AM6254	OSPI0_CSN0	F19
OSPI0_CSN1	C25	AM6254	OSPI0_CSN1	F17
OSPI0_CSN2	D24	AM6254	OSPI0_CSN2	E17
OSPI0_CSN3	C24	AM6254	OSPI0_CSN3	E18
OSPI0_D0	B24	AM6254	OSPI0_D0	F18
OSPI0_D1	A25	AM6254	OSPI0_D1	G17
OSPI0_D2	B25	AM6254	OSPI0_D2	F21
OSPI0_D3	A26	AM6254	OSPI0_D3	F20
OSPI0_D4	B26	AM6254	OSPI0_D4	G21
OSPI0_D5	B27	AM6254	OSPI0_D5	H21
OSPI0_D6	C27	AM6254	OSPI0_D6	G20
OSPI0_D7	C28	AM6254	OSPI0_D7	J21
OSPI0_DQS	D26	AM6254	OSPI0_DQS	H20
OSPI0_LBCLKO	C26	AM6254	OSPI0_LBCLKO	G18
PMIC_LPM_EN0	D5	AM6254	PMIC_LPM_EN0	C7
PORZ_OUT	D18	AM6254	PORZ_OUT	E13
RESET_REQZ	D17	AM6254	RESET_REQZ	E15
RESETSTATZ	C18	AM6254	RESETSTATZ	E14
RGMII1_RD0	U22	AM6254	RGMII1_RD0	W15
RGMII1_RD1	V22	AM6254	RGMII1_RD1	Y16
RGMII1_RD2	U21	AM6254	RGMII1_RD2	AA17
RGMII1_RD3	V21	AM6254	RGMII1_RD3	Y15
RGMII1_RX_CTL	V20	AM6254	RGMII1_RX_CTL	W14
RGMII1_RXC	U20	AM6254	RGMII1_RXC	AA16
RGMII1_TD0	U25	AM6254	RGMII1_TD0	U14
RGMII1_TD1	V25	AM6254	RGMII1_TD1	AA19
RGMII1_TD2	U24	AM6254	RGMII1_TD2	Y17
RGMII1_TD3	V24	AM6254	RGMII1_TD3	AA18
RGMII1_TX_CTL	V23	AM6254	RGMII1_TX_CTL	V15
RGMII1_TXC	U23	AM6254	RGMII1_TXC	W16
RGMII2_RD0	T25	AM6254	RGMII2_RD0	W18
RGMII2_RD1	R24	AM6254	RGMII2_RD1	Y20
RGMII2_RD2	T24	AM6254	RGMII2_RD2	Y19
RGMII2_RD3	R23	AM6254	RGMII2_RD3	W20
RGMII2_RX_CTL	T23	AM6254	RGMII2_RX_CTL	W19
RGMII2_RXC	R22	AM6254	RGMII2_RXC	V18
RGMII2_TD0	T22	AM6254	RGMII2_TD0	AA20
RGMII2_TD1	R21	AM6254	RGMII2_TD1	U15
RGMII2_TD2	T21	AM6254	RGMII2_TD2	W17
RGMII2_TD3	R20	AM6254	RGMII2_TD3	V16
RGMII2_TX_CTL	T20	AM6254	RGMII2_TX_CTL	Y21
RGMII2_TXC	R19	AM6254	RGMII2_TXC	Y18
SPI0_CLK	C11	AM6254	SPI0_CLK	D12
SPI0_CS0	D13	AM6254	SPI0_CS0	C11
SPI0_CS1	C13	AM6254	SPI0_CS1	D13
SPI0_D0	D12	AM6254	SPI0_D0	C12
SPI0_D1	C12	AM6254	SPI0_D1	A14
TCK	D9	AM6254	TCK	C10
TDI	D10	AM6254	TDI	D10
TDO	D11	AM6254	TDO	E10
TMS	C10	AM6254	TMS	B11
TRSTN	C9	AM6254	TRSTN	A11
UART0_CTSN	A9	AM6254	UART0_CTSN	B14
UART0_RTSN	B9	AM6254	UART0_RTSN	C13
UART0_RXD	A10	AM6254	UART0_RXD	A13
UART0_TXD	B10	AM6254	UART0_TXD	E11
USB0_DM	U12	AM6254	USB0_DM	AA11
USB0_DP	V12	AM6254	USB0_DP	Y10
USB0_DRVVBUS	C19	AM6254	USB0_DRVVBUS	D17
USB0_VBUS	V11	AM6254	USB0_VBUS	V10
USB1_DM	U10	AM6254	USB1_DM	W8
USB1_DP	V10	AM6254	USB1_DP	W9
USB1_DRVVBUS	D19	AM6254	USB1_DRVVBUS	E16
USB1_VBUS	U11	AM6254	USB1_VBUS	U9
VDD_CANUART	G12	AM6254	VDD_CANUART	H8
VDD_CORE	G13	AM6254	VDD_CORE / VDDA_DDR_PLL0	See Note (3)
VDD_CORE	G14	AM6254	VDD_CORE / VDDA_DDR_PLL0	See Note (3)
VDD_CORE	G15	AM6254	VDD_CORE / VDDA_DDR_PLL0	See Note (3)
VDD_CORE	G16	AM6254	VDD_CORE / VDDA_DDR_PLL0	See Note (3)
VDD_CORE	H12	AM6254	VDD_CORE / VDDA_DDR_PLL0	See Note (3)
VDD_CORE	H13	AM6254	VDD_CORE / VDDA_DDR_PLL0	See Note (3)
VDD_CORE	H14	AM6254	VDD_CORE / VDDA_DDR_PLL0	See Note (3)
VDD_CORE	H15	AM6254	VDD_CORE / VDDA_DDR_PLL0	See Note (3)
VDD_CORE	H16	AM6254	VDD_CORE / VDDA_DDR_PLL0	See Note (3)
VDD_CORE	J12	AM6254	VDD_CORE / VDDA_DDR_PLL0	See Note (3)
VDD_CORE	J13	AM6254	VDD_CORE / VDDA_DDR_PLL0	See Note (3)
VDD_CORE	J16	AM6254	VDD_CORE / VDDA_DDR_PLL0	See Note (3)
VDD_CORE	K12	AM6254	VDD_CORE / VDDA_DDR_PLL0	See Note (3)
VDD_CORE	K13	AM6254	VDD_CORE / VDDA_DDR_PLL0	See Note (3)
VDD_CORE	K16	AM6254	VDD_CORE / VDDA_DDR_PLL0	See Note (3)
VDD_CORE	L13	AM6254	VDD_CORE / VDDA_DDR_PLL0	See Note (3)
VDD_CORE	L14	AM6254	VDD_CORE / VDDA_DDR_PLL0	See Note (3)
VDD_CORE	L15	AM6254	VDD_CORE / VDDA_DDR_PLL0	See Note (3)
VDDA_1P8_CSIRX0	P13	AM6254	VDDA_1P8_CSIRX0	R12
VDDA_1P8_OLDI0	P11	AM6254	VDDA_1P8_OLDI0	P9, R9
VDDA_1P8_USB	P12	AM6254	VDDA_1P8_USB	R11
VDDA_3P3_USB	N7	AM6254	VDDA_3P3_USB	R10
VDDA_CORE_CSIRX0	M13	AM6254	VDDA_CORE_CSIRX0	P12
VDDA_CORE_USB	M12	AM6254	VDDA_CORE_USB	P11
VDDA_MCU	F13	AM6254	VDDA_MCU	H10
VDDA_PLL0	N13	AM6254	VDDA_PLL0	N10
VDDA_PLL1	N14	AM6254	VDDA_PLL1	P14
VDDA_PLL2	F14	AM6254	VDDA_PLL2	K12
VDDA_TEMP	N12	AM6254	VDDA_TEMP0 / VDDA_TEMP1	M7, F16
VDDR_CORE	H17	AM6254	VDDR_CORE	H11, M10, M13
VDDR_CORE	H18	AM6254	VDDR_CORE	H11, M10, M13
VDDR_CORE	J17	AM6254	VDDR_CORE	H11, M10, M13
VDDR_CORE	J18	AM6254	VDDR_CORE	H11, M10, M13
VDDR_CORE	K17	AM6254	VDDR_CORE	H11, M10, M13
VDDR_CORE	K18	AM6254	VDDR_CORE	H11, M10, M13
VDDR_CORE	L17	AM6254	VDDR_CORE	H11, M10, M13
VDDR_CORE	L18	AM6254	VDDR_CORE	H11, M10, M13
VDDS_DDR	K10	AM6254	VDDS_DDR / VDDS_DDR_C	C1, J8, K7, K9, L8, U1, L7
VDDS_DDR	K11	AM6254	VDDS_DDR / VDDS_DDR_C	C1, J8, K7, K9, L8, U1, L7
VDDS_DDR	L9	AM6254	VDDS_DDR / VDDS_DDR_C	C1, J8, K7, K9, L8, U1, L7
VDDS_DDR	L10	AM6254	VDDS_DDR / VDDS_DDR_C	C1, J8, K7, K9, L8, U1, L7
VDDS_DDR	L11	AM6254	VDDS_DDR / VDDS_DDR_C	C1, J8, K7, K9, L8, U1, L7
VDDS_DDR	M8	AM6254	VDDS_DDR / VDDS_DDR_C	C1, J8, K7, K9, L8, U1, L7
VDDS_DDR	M9	AM6254	VDDS_DDR / VDDS_DDR_C	C1, J8, K7, K9, L8, U1, L7
VDDS_DDR	M10	AM6254	VDDS_DDR / VDDS_DDR_C	C1, J8, K7, K9, L8, U1, L7
VDDS_DDR	N8	AM6254	VDDS_DDR / VDDS_DDR_C	C1, J8, K7, K9, L8, U1, L7
VDDS_DDR	N9	AM6254	VDDS_DDR / VDDS_DDR_C	C1, J8, K7, K9, L8, U1, L7
VDDS_OSC0	D15	AM6254	VDDS_OSC0	J7
VDDSHV0	J21	AM6254	VDDSHV0	F12, G13
VDDSHV0	J22	AM6254	VDDSHV0	F12, G13
VDDSHV1	K21	AM6254	VDDSHV1	K15, K16
VDDSHV1	K22	AM6254	VDDSHV1	K15, K16
VDDSHV2	M21	AM6254	VDDSHV2	R14, R15
VDDSHV2	M22	AM6254	VDDSHV2	R14, R15
VDDSHV3	L21	AM6254	VDDSHV3	N15, N16
VDDSHV3	L22	AM6254	VDDSHV3	N15, N16
VDDSHV4	N11	AM6254	VDDSHV4	N7, P7
VDDSHV4	P10	AM6254	VDDSHV4	N7, P7
VDDSHV5	G21	AM6254	VDDSHV5	F14, G14
VDDSHV5	G22	AM6254	VDDSHV5	F14, G14
VDDSHV6	H21	AM6254	VDDSHV6	H15, H16
VDDSHV6	H22	AM6254	VDDSHV6	H15, H16
VDDSHV_CANUART	F11	AM6254	VDDSHV_CANUART	G7, H7
VDDSHV_CANUART	G10	AM6254	VDDSHV_CANUART	G7, H7
VDDSHV_MCU	F12	AM6254	VDDSHV_MCU	F10, G10
VDDSHV_MCU	G11	AM6254	VDDSHV_MCU	F10, G10
VMON_1P8_SOC	C15	AM6254	VMON_1P8_SOC	H9
VMON_3P3_SOC	B15	AM6254	VMON_3P3_SOC	K11
VMON_VSYS	A15	AM6254	VMON_VSYS	F6
VOUT0_DATA0	P26	AM6254	VOUT0_DATA0	R21
VOUT0_DATA1	N25	AM6254	VOUT0_DATA1	P18
VOUT0_DATA10	P27	AM6254	VOUT0_DATA10	T18
VOUT0_DATA11	P28	AM6254	VOUT0_DATA11	U20
VOUT0_DATA12	N27	AM6254	VOUT0_DATA12	U19
VOUT0_DATA13	N28	AM6254	VOUT0_DATA13	V21
VOUT0_DATA14	M27	AM6254	VOUT0_DATA14	U18
VOUT0_DATA15	M28	AM6254	VOUT0_DATA15	V20
VOUT0_DATA2	N26	AM6254	VOUT0_DATA2	R18
VOUT0_DATA3	M25	AM6254	VOUT0_DATA3	R19
VOUT0_DATA4	M26	AM6254	VOUT0_DATA4	R20
VOUT0_DATA5	U27	AM6254	VOUT0_DATA5	T20
VOUT0_DATA6	T27	AM6254	VOUT0_DATA6	T21
VOUT0_DATA7	T28	AM6254	VOUT0_DATA7	T19
VOUT0_DATA8	R27	AM6254	VOUT0_DATA8	U21
VOUT0_DATA9	R28	AM6254	VOUT0_DATA9	R17
VOUT0_DE	R25	AM6254	VOUT0_DE	T17
VOUT0_HSYNC	P25	AM6254	VOUT0_HSYNC	W21
VOUT0_PCLK	T26	AM6254	VOUT0_PCLK	U17
VOUT0_VSYNC	R26	AM6254	VOUT0_VSYNC	T16
VPP	C16	AM6254	VPP	F7
VSS	A2	AM6254	VSS	See Note (1)
VSS	A14	AM6254	VSS	See Note (1)
VSS	A27	AM6254	VSS	See Note (1)
VSS	B1	AM6254	VSS	See Note (1)
VSS	B14	AM6254	VSS	See Note (1)
VSS	B28	AM6254	VSS	See Note (1)
VSS	C3	AM6254	VSS	See Note (1)
VSS	C4	AM6254	VSS	See Note (1)
VSS	C14	AM6254	VSS	See Note (1)
VSS	D3	AM6254	VSS	See Note (1)
VSS	D4	AM6254	VSS	See Note (1)
VSS	D14	AM6254	VSS	See Note (1)
VSS	E3	AM6254	VSS	See Note (1)
F22	AM6254	VSS	See Note (1)
VSS	F23	AM6254	VSS	See Note (1)
VSS	F24	AM6254	VSS	See Note (1)
VSS	G19	AM6254	VSS	See Note (1)
VSS	G20	AM6254	VSS	See Note (1)
VSS	G23	AM6254	VSS	See Note (1)
VSS	G24	AM6254	VSS	See Note (1)
VSS	H19	AM6254	VSS	See Note (1)
VSS	H20	AM6254	VSS	See Note (1)
VSS	H24	AM6254	VSS	See Note (1)
VSS	J14	AM6254	VSS	See Note (1)
VSS	J15	AM6254	VSS	See Note (1)
VSS	J19	AM6254	VSS	See Note (1)
VSS	J20	AM6254	VSS	See Note (1)
VSS	J24	AM6254	VSS	See Note (1)
VSS	K6	AM6254	VSS	See Note (1)
VSS	K7	AM6254	VSS	See Note (1)
VSS	K8	AM6254	VSS	See Note (1)
VSS	K9	AM6254	VSS	See Note (1)
VSS	K14	AM6254	VSS	See Note (1)
VSS	K15	AM6254	VSS	See Note (1)
VSS	K19	AM6254	VSS	See Note (1)
VSS	K20	AM6254	VSS	See Note (1)
VSS	K24	AM6254	VSS	See Note (1)
VSS	L5	AM6254	VSS	See Note (1)
VSS	L6	AM6254	VSS	See Note (1)
VSS	L7	AM6254	VSS	See Note (1)
VSS	L8	AM6254	VSS	See Note (1)
VSS	L19	AM6254	VSS	See Note (1)
VSS	L20	AM6254	VSS	See Note (1)
VSS	L24	AM6254	VSS	See Note (1)
VSS	M4	AM6254	VSS	See Note (1)
VSS	M5	AM6254	VSS	See Note (1)
VSS	M6	AM6254	VSS	See Note (1)
VSS	M7	AM6254	VSS	See Note (1)
VSS	M20	AM6254	VSS	See Note (1)
VSS	M23	AM6254	VSS	See Note (1)
VSS	M24	AM6254	VSS	See Note (1)
VSS	N3	AM6254	VSS	See Note (1)
VSS	N4	AM6254	VSS	See Note (1)
VSS	N5	AM6254	VSS	See Note (1)
VSS	N6	AM6254	VSS	See Note (1)
VSS	N20	AM6254	VSS	See Note (1)
VSS	N21	AM6254	VSS	See Note (1)
VSS	N22	AM6254	VSS	See Note (1)
VSS	N23	AM6254	VSS	See Note (1)
VSS	N24	AM6254	VSS	See Note (1)
VSS	P3	AM6254	VSS	See Note (1)
VSS	P4	AM6254	VSS	See Note (1)
VSS	P5	AM6254	VSS	See Note (1)
VSS	P16	AM6254	VSS	See Note (1)
VSS	P17	AM6254	VSS	See Note (1)
VSS	P18	AM6254	VSS	See Note (1)
VSS	P19	AM6254	VSS	See Note (1)
VSS	P20	AM6254	VSS	See Note (1)
VSS	P21	AM6254	VSS	See Note (1)
VSS	P22	AM6254	VSS	See Note (1)
VSS	P23	AM6254	VSS	See Note (1)
VSS	P24	AM6254	VSS	See Note (1)
VSS	R3	AM6254	VSS	See Note (1)
VSS	R4	AM6254	VSS	See Note (1)
VSS	T3	AM6254	VSS	See Note (1)
VSS	T19	AM6254	VSS	See Note (1)
VSS	U1	AM6254	VSS	See Note (1)
VSS	U19	AM6254	VSS	See Note (1)
VSS	U28	AM6254	VSS	See Note (1)
VSS	V2	AM6254	VSS	See Note (1)
VSS	V19	AM6254	VSS	See Note (1)
VSS	V27	AM6254	VSS	See Note (1)
WKUP_CLKOUT0	C7	AM6254	WKUP_CLKOUT0	B12
WKUP_I2C0_SCL	A8	AM6254	WKUP_I2C0_SCL	E9
WKUP_I2C0_SDA	B8	AM6254	WKUP_I2C0_SDA	A9
WKUP_LFOSC0_XI	H1	AM6254	WKUP_LFOSC0_XI	A2
WKUP_LFOSC0_XO	H2	AM6254	WKUP_LFOSC0_XO	A3
WKUP_UART0_CTSN	D1	AM6254	WKUP_UART0_CTSN	A7
WKUP_UART0_RTSN	D2	AM6254	WKUP_UART0_RTSN	B4
WKUP_UART0_RXD	C2	AM6254	WKUP_UART0_RXD	B5
WKUP_UART0_TXD	C1	AM6254	WKUP_UART0_TXD	C6

Notes:

(1)	See VSS pin in AM6254 Datasheet	A1, A21, A4, AA1, AA12, AA15, AA21, AA9, D11, D19, D4, E2, F11, F13, F15, F4, F9, G16, G6, G9, H1, H13, H6, J10, J12, J14, J16, J6, K13, K3, K6, K8, L1, L10, L12, L14, L16, L6, M11, M16, M18, M6, M9, N12, N14, N6, P1, P10, P13, P15, P16, P3, P6, R16, R5, R7, R8, T10, T12, T15, T3, T6, T7, T9, U10, U13, U5, U8, V11, V14, V19, W10, W13, W7, Y11, Y14, Y3, Y4, Y6
(2)	See NC pin in AM6254 Datasheet	There are no No Connect pins on the AM6254 AMC package
(3)	See VDD_CORE / VDDA_DDR_PLL0 pin in the AM6254 Datasheet	H12, H14, J11, J13, J9, K10, K14, L11, L13, M12, M14, M8, N11, N13, N9, P8, L9

AM6254 to OSD62x-PM Pin Mapping

Discrete Device	Discrete Signal Name	Discrete Pin Number	SiP Signal Name	SiP Pins	Notes
AM6254	CAP_VDDS0	G12	NA	NA	Pin connected to capacitor within OSD62x-PM
AM6254	CAP_VDDS1	L15	NA	NA	Pin connected to capacitor within OSD62x-PM
AM6254	CAP_VDDS2	R13	NA	NA	Pin connected to capacitor within OSD62x-PM
AM6254	CAP_VDDS3	M15	NA	NA	Pin connected to capacitor within OSD62x-PM
AM6254	CAP_VDDS4	N8	NA	NA	Pin connected to capacitor within OSD62x-PM
AM6254	CAP_VDDS5	G15	NA	NA	Pin connected to capacitor within OSD62x-PM
AM6254	CAP_VDDS6	J15	NA	NA	Pin connected to capacitor within OSD62x-PM
AM6254	CAP_VDDS_CANUART	G8	NA	NA	Pin connected to capacitor within OSD62x-PM
AM6254	CAP_VDDS_MCU	G11	NA	NA	Pin connected to capacitor within OSD62x-PM
AM6254	CSI0_RXCLKN	AA14	CSI0_RXCLKN	V17
AM6254	CSI0_RXCLKP	AA13	CSI0_RXCLKP	U17
AM6254	CSI0_RXRCALIB	T11	NA	NA	Pin connected to resistor within OSD62x-PM
AM6254	CSI0_RXN0	Y13	CSI0_RXN0	V16
AM6254	CSI0_RXN1	V13	CSI0_RXN1	V15
AM6254	CSI0_RXN2	U12	CSI0_RXN2	U14
AM6254	CSI0_RXN3	W12	CSI0_RXN3	U13
AM6254	CSI0_RXP0	Y12	CSI0_RXP0	U16
AM6254	CSI0_RXP1	V12	CSI0_RXP1	U15
AM6254	CSI0_RXP2	U11	CSI0_RXP2	V14
AM6254	CSI0_RXP3	W11	CSI0_RXP3	V13
AM6254	DDR0_ACT_n	M1	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_ALERT_n	N1	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_CAS_n	J3	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_PAR	M2	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_RAS_n	K5	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_WE_n	J2	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_A0	F5	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_A1	G5	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_A2	G4	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_A3	H4	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_A4	J5	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_A5	H5	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_A6	P4	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_A7	N2	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_A8	P2	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_A9	N4	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_A10	N3	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_A11	M3	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_A12	P5	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_A13	N5	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_BA0	L5	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_BA1	L3	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_BG0	L4	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_BG1	L2	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_CAL0	K4	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_CK0	J1	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_CK0_n	K1	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_CKE0	G3	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_CKE1	H2	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_CS0_n	H3	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_CS1_n	G1	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_DM0	E3	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_DM1	R4	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_DQ0	C2	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_DQ1	E4	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_DQ2	D3	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_DQ3	E5	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_DQ4	D2	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_DQ5	F3	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_DQ6	F1	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_DQ7	F2	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_DQ8	R3	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_DQ9	R2	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_DQ10	T2	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_DQ11	U2	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_DQ12	U3	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_DQ13	U4	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_DQ14	T4	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_DQ15	T5	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_DQS0	D1	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_DQS0_n	E1	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_DQS1	T1	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_DQS1_n	R1	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_ODT0	J4	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_ODT1	K2	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	DDR0_RESET0_n	G2	NA	NA	Pin connected to DDR within OSD62x-PM
AM6254	EMU0	D9	EMU0	D8
AM6254	EMU1	B10	EMU1	C8
AM6254	EXTINTn	B16	EXTINTN	C17
AM6254	EXT_REFCLK1	C14	EXT_REFCLK1	D16
AM6254	GPMC0_ADVn_ALE	K20	GPMC0_ADVn_ALE	H25
AM6254	GPMC0_CLK	M19	GPMC0_CLK	K26
AM6254	GPMC0_DIR	J19	GPMC0_DIR	G25
AM6254	GPMC0_OEn_Ren	K21	GPMC0_OEN_REN	H26
AM6254	GPMC0_Wen	J17	GPMC0_WEN	J25
AM6254	GPMC0_WPn	J20	GPMC0_WPN	G26
AM6254	GPMC0_AD0	K19	GPMC0_AD0	G28
AM6254	GPMC0_AD1	L19	GPMC0_AD1	G27
AM6254	GPMC0_AD2	L20	GPMC0_AD2	F28
AM6254	GPMC0_AD3	L21	GPMC0_AD3	F27
AM6254	GPMC0_AD4	M21	GPMC0_AD4	E28
AM6254	GPMC0_AD5	L17	GPMC0_AD5	E27
AM6254	GPMC0_AD6	L18	GPMC0_AD6	D28
AM6254	GPMC0_AD7	M20	GPMC0_AD7	D27
AM6254	GPMC0_AD8	N20	GPMC0_AD8	L27
AM6254	GPMC0_AD9	N21	GPMC0_AD9	L28
AM6254	GPMC0_AD10	M17	GPMC0_AD10	K27
AM6254	GPMC0_AD11	N18	GPMC0_AD11	K28
AM6254	GPMC0_AD12	N17	GPMC0_AD12	J28
AM6254	GPMC0_AD13	N19	GPMC0_AD13	J27
AM6254	GPMC0_AD14	P19	GPMC0_AD14	H28
AM6254	GPMC0_AD15	P20	GPMC0_AD15	H27
AM6254	GPMC0_BE0n_CLE	K17	GPMC0_BE0N_CLE	J26
AM6254	GPMC0_BE1n	K18	GPMC0_BE1N	K25
AM6254	GPMC0_CSn0	J18	GPMC0_CSN0	F26
AM6254	GPMC0_CSn1	H17	GPMC0_CSN1	F25
AM6254	GPMC0_CSn2	H18	GPMC0_CSN2	E26
AM6254	GPMC0_CSn3	H19	GPMC0_CSN3	E25
AM6254	GPMC0_WAIT0	P21	GPMC0_WAIT0	L25
AM6254	GPMC0_WAIT1	P17	GPMC0_WAIT1	L26
AM6254	I2C0_SCL	E12	I2C0_SCL	A12
AM6254	I2C0_SDA	D14	I2C0_SDA	B12
AM6254	I2C1_SCL	A17	I2C1_SCL	A13
AM6254	I2C1_SDA	A16	I2C1_SDA	B13
AM6254	MCAN0_RX	A15	MCAN0_RX	A11
AM6254	MCAN0_TX	B13	MCAN0_TX	B11
AM6254	MCASP0_ACLKR	D16	MCASP0_ACLKR	B19
AM6254	MCASP0_ACLKX	C17	MCASP0_ACLKX	A18
AM6254	MCASP0_AFSR	D15	MCASP0_AFSR	A19
AM6254	MCASP0_AFSX	C16	MCASP0_AFSX	B18
AM6254	MCASP0_AXR0	D18	MCASP0_AXR0	B17
AM6254	MCASP0_AXR1	A18	MCASP0_AXR1	A17
AM6254	MCASP0_AXR2	B17	MCASP0_AXR2	B16
AM6254	MCASP0_AXR3	B18	MCASP0_AXR3	A16
AM6254	MCU_ERRORn	B1	MCU_ERRORN	D7
AM6254	MCU_I2C0_SCL	B9	MCU_I2C0_SCL	A7
AM6254	MCU_I2C0_SDA	A10	MCU_I2C0_SDA	B7
AM6254	MCU_MCAN0_RX	C4	MCU_MCAN0_RX	E1
AM6254	MCU_MCAN0_TX	C5	MCU_MCAN0_TX	E2
AM6254	MCU_MCAN1_RX	D6	MCU_MCAN1_RX	F1
AM6254	MCU_MCAN1_TX	D5	MCU_MCAN1_TX	F2
AM6254	MCU_OSC0_XI	A5	MCU_OSC0_XI	G1
AM6254	MCU_OSC0_XO	A6	MCU_OSC0_XO	G2
AM6254	MCU_PORz	B2	MCU_PORZ	D6
AM6254	MCU_RESETSTATz	A12	MCU_RESETSTATZ	C6
AM6254	MCU_RESETz	C9	MCU_RESETZ	C5
AM6254	MCU_SPI0_CLK	B7	MCU_SPI0_CLK	A4
AM6254	MCU_SPI0_CS0	E7	MCU_SPI0_CS0	B6
AM6254	MCU_SPI0_CS1	C8	MCU_SPI0_CS1	A6
AM6254	MCU_SPI0_D0	E8	MCU_SPI0_D0	B5
AM6254	MCU_SPI0_D1	D8	MCU_SPI0_D1	A5
AM6254	MCU_UART0_CTSn	B8	MCU_UART0_CTSN	B4
AM6254	MCU_UART0_RTSn	D7	MCU_UART0_RTSN	A3
AM6254	MCU_UART0_RXD	A8	MCU_UART0_RXD	B2
AM6254	MCU_UART0_TXD	B6	MCU_UART0_TXD	B3
AM6254	MDIO0_MDC	V17	MDIO0_MDC	V26
AM6254	MDIO0_MDIO	U16	MDIO0_MDIO	U26
AM6254	MMC0_CLK	Y1	MMC0_CLK	J1
AM6254	MMC0_CMD	V3	MMC0_CMD	K1
AM6254	MMC1_CLK	A20	MMC1_CLK	B21
AM6254	MMC1_CMD	C18	MMC1_CMD	A21
AM6254	MMC1_SDCD	C15	MMC1_SDCD	A23
AM6254	MMC1_SDWP	B15	MMC1_SDWP	B23
AM6254	MMC2_CLK	E21	MMC2_CLK	D23
AM6254	MMC2_CMD	C21	MMC2_CMD	C23
AM6254	MMC2_SDCD	D20	MMC2_SDCD	D20
AM6254	MMC2_SDWP	C20	MMC2_SDWP	C20
AM6254	MMC0_DAT0	V2	MMC0_DAT0	K2
AM6254	MMC0_DAT1	V1	MMC0_DAT1	L1
AM6254	MMC0_DAT2	W2	MMC0_DAT2	L2
AM6254	MMC0_DAT3	W1	MMC0_DAT3	M1
AM6254	MMC0_DAT4	Y2	MMC0_DAT4	M2
AM6254	MMC0_DAT5	W3	MMC0_DAT5	N1
AM6254	MMC0_DAT6	W4	MMC0_DAT6	N2
AM6254	MMC0_DAT7	V4	MMC0_DAT7	P1
AM6254	MMC1_DAT0	A19	MMC1_DAT0	A22
AM6254	MMC1_DAT1	B19	MMC1_DAT1	B22
AM6254	MMC1_DAT2	B20	MMC1_DAT2	A20
AM6254	MMC1_DAT3	C19	MMC1_DAT3	B20
AM6254	MMC2_DAT0	B21	MMC2_DAT0	D22
AM6254	MMC2_DAT1	D21	MMC2_DAT1	C22
AM6254	MMC2_DAT2	E19	MMC2_DAT2	D21
AM6254	MMC2_DAT3	E20	MMC2_DAT3	C21
AM6254	OLDI0_A0N	AA2	OLDI0_A0N	P2
AM6254	OLDI0_A0P	AA3	OLDI0_A0P	R1
AM6254	OLDI0_A1N	V5	OLDI0_A1N	R2
AM6254	OLDI0_A1P	V6	OLDI0_A1P	T1
AM6254	OLDI0_A2N	U7	OLDI0_A2N	T2
AM6254	OLDI0_A2P	U6	OLDI0_A2P	U2
AM6254	OLDI0_A3N	W6	OLDI0_A3N	U3
AM6254	OLDI0_A3P	W5	OLDI0_A3P	V3
AM6254	OLDI0_A4N	AA4	OLDI0_A4N	U4
AM6254	OLDI0_A4P	Y5	OLDI0_A4P	V4
AM6254	OLDI0_A5N	AA6	OLDI0_A5N	U5
AM6254	OLDI0_A5P	AA5	OLDI0_A5P	V5
AM6254	OLDI0_A6N	AA10	OLDI0_A6N	U6
AM6254	OLDI0_A6P	Y9	OLDI0_A6P	V6
AM6254	OLDI0_A7N	AA8	OLDI0_A7N	U7
AM6254	OLDI0_A7P	Y8	OLDI0_A7P	V7
AM6254	OLDI0_CLK0N	V7	OLDI0_CLK0N	U8
AM6254	OLDI0_CLK0P	V8	OLDI0_CLK0P	V8
AM6254	OLDI0_CLK1N	Y7	OLDI0_CLK1N	U9
AM6254	OLDI0_CLK1P	AA7	OLDI0_CLK1P	V9
AM6254	OSPI0_CLK	G19	OSPI0_CLK	A24
AM6254	OSPI0_DQS	H20	OSPI0_DQS	D26
AM6254	OSPI0_LBCLKO	G18	OSPI0_LBCLKO	C26
AM6254	OSPI0_CSn0	F19	OSPI0_CSN0	D25
AM6254	OSPI0_CSn1	F17	OSPI0_CSN1	C25
AM6254	OSPI0_CSn2	E17	OSPI0_CSN2	D24
AM6254	OSPI0_CSn3	E18	OSPI0_CSN3	C24
AM6254	OSPI0_D0	F18	OSPI0_D0	B24
AM6254	OSPI0_D1	G17	OSPI0_D1	A25
AM6254	OSPI0_D2	F21	OSPI0_D2	B25
AM6254	OSPI0_D3	F20	OSPI0_D3	A26
AM6254	OSPI0_D4	G21	OSPI0_D4	B26
AM6254	OSPI0_D5	H21	OSPI0_D5	B27
AM6254	OSPI0_D6	G20	OSPI0_D6	C27
AM6254	OSPI0_D7	J21	OSPI0_D7	C28
AM6254	PMIC_LPM_EN0	C7	PMIC_LPM_EN0	D5
AM6254	PORz_OUT	E13	PORZ_OUT	D18
AM6254	RESETSTATz	E14	RESETSTATZ	C18
AM6254	RESET_REQz	E15	RESET_REQZ	D17
AM6254	RGMII1_RXC	AA16	RGMII1_RXC	U20
AM6254	RGMII1_RX_CTL	W14	RGMII1_RX_CTL	V20
AM6254	RGMII1_TXC	W16	RGMII1_TXC	U23
AM6254	RGMII1_TX_CTL	V15	RGMII1_TX_CTL	V23
AM6254	RGMII2_RXC	V18	RGMII2_RXC	R22
AM6254	RGMII2_RX_CTL	W19	RGMII2_RX_CTL	T23
AM6254	RGMII2_TXC	Y18	RGMII2_TXC	R19
AM6254	RGMII2_TX_CTL	Y21	RGMII2_TX_CTL	T20
AM6254	RGMII1_RD0	W15	RGMII1_RD0	U22
AM6254	RGMII1_RD1	Y16	RGMII1_RD1	V22
AM6254	RGMII1_RD2	AA17	RGMII1_RD2	U21
AM6254	RGMII1_RD3	Y15	RGMII1_RD3	V21
AM6254	RGMII1_TD0	U14	RGMII1_TD0	U25
AM6254	RGMII1_TD1	AA19	RGMII1_TD1	V25
AM6254	RGMII1_TD2	Y17	RGMII1_TD2	U24
AM6254	RGMII1_TD3	AA18	RGMII1_TD3	V24
AM6254	RGMII2_RD0	W18	RGMII2_RD0	T25
AM6254	RGMII2_RD1	Y20	RGMII2_RD1	R24
AM6254	RGMII2_RD2	Y19	RGMII2_RD2	T24
AM6254	RGMII2_RD3	W20	RGMII2_RD3	R23
AM6254	RGMII2_TD0	AA20	RGMII2_TD0	T22
AM6254	RGMII2_TD1	U15	RGMII2_TD1	R21
AM6254	RGMII2_TD2	W17	RGMII2_TD2	T21
AM6254	RGMII2_TD3	V16	RGMII2_TD3	R20
AM6254	RSVD0	B3	AM62X_RSVD0	F5
AM6254	RSVD1	C3	AM62X_RSVD1	F4
AM6254	RSVD2	E6	AM62X_RSVD2	F6
AM6254	RSVD3	F8	AM62X_RSVD3	N17
AM6254	RSVD4	R6	AM62X_RSVD4	F8
AM6254	RSVD5	T13	AM62X_RSVD5	F9
AM6254	RSVD6	T14	AM62X_RSVD6	M18
AM6254	RSVD7	M4	AM62X_RSVD7	N18
AM6254	RSVD8	M5	AM62X_RSVD8	F7
AM6254	SPI0_CLK	D12	SPI0_CLK	C11
AM6254	SPI0_CS0	C11	SPI0_CS0	D13
AM6254	SPI0_CS1	D13	SPI0_CS1	C13
AM6254	SPI0_D0	C12	SPI0_D0	D12
AM6254	SPI0_D1	A14	SPI0_D1	C12
AM6254	TCK	C10	TCK	D9
AM6254	TDI	D10	TDI	D10
AM6254	TDO	E10	TDO	D11
AM6254	TMS	B11	TMS	C10
AM6254	TRSTn	A11	TRSTN	C9
AM6254	UART0_CTSn	B14	UART0_CTSN	A9
AM6254	UART0_RTSn	C13	UART0_RTSN	B9
AM6254	UART0_RXD	A13	UART0_RXD	A10
AM6254	UART0_TXD	E11	UART0_TXD	B10
AM6254	USB0_DM	AA11	USB0_DM	U12
AM6254	USB0_DP	Y10	USB0_DP	V12
AM6254	USB0_DRVVBUS	D17	USB0_DRVVBUS	C19
AM6254	USB0_RCALIB	T8	NA	NA	Pin connected to resistor within OSD62x-PM
AM6254	USB0_VBUS	V10	USB0_VBUS	V11
AM6254	USB1_DM	W8	USB1_DM	U10
AM6254	USB1_DP	W9	USB1_DP	V10
AM6254	USB1_DRVVBUS	E16	USB1_DRVVBUS	D19
AM6254	USB1_RCALIB	V9	NA	NA	Pin connected to resistor within OSD62x-PM
AM6254	USB1_VBUS	U9	USB1_VBUS	U11
AM6254	VDDA_1P8_USB	R11	VDDA_1P8_USB	P12
AM6254	VDDA_1P8_CSIRX0	R12	VDDA_1P8_CSIRX0	P13
AM6254	VDDA_1P8_OLDI0	P9	VDDA_1P8_OLDI0	P11
AM6254	VDDA_1P8_OLDI0	R9	VDDA_1P8_OLDI0	P11
AM6254	VDDA_3P3_USB	R10	VDDA_3P3_USB	N7
AM6254	VDDA_CORE_CSIRX0	P12	VDDA_CORE_CSIRX0	M13
AM6254	VDDA_CORE_USB	P11	VDDA_CORE_USB	M12
AM6254	VDDA_DDR_PLL0	L9	VDD_CORE	See Note (3)
AM6254	VDDA_MCU	H10	VDDA_MCU	F13
AM6254	VDDA_PLL0	N10	VDDA_PLL0	N13
AM6254	VDDA_PLL1	P14	VDDA_PLL1	N14
AM6254	VDDA_PLL2	K12	VDDA_PLL2	F14
AM6254	VDDA_TEMP0	M7	VDDA_TEMP	N12
AM6254	VDDA_TEMP1	F16	VDDA_TEMP	N12
AM6254	VDDR_CORE	H11	VDDR_CORE	See Note (4)
AM6254	VDDR_CORE	M10	VDDR_CORE	See Note (4)
AM6254	VDDR_CORE	M13	VDDR_CORE	See Note (4)
AM6254	VDDSHV0	F12	VDDSHV0	J21, J22
AM6254	VDDSHV0	G13	VDDSHV0	J21, J22
AM6254	VDDSHV1	K15	VDDSHV1	K21, K22
AM6254	VDDSHV1	K16	VDDSHV1	K21, K22
AM6254	VDDSHV2	R14	VDDSHV2	M21, M22
AM6254	VDDSHV2	R15	VDDSHV2	M21, M22
AM6254	VDDSHV3	N15	VDDSHV3	L21, L22
AM6254	VDDSHV3	N16	VDDSHV3	L21, L22
AM6254	VDDSHV4	N7	VDDSHV4	N11, P10
AM6254	VDDSHV4	P7	VDDSHV4	N11, P10
AM6254	VDDSHV5	F14	VDDSHV5	G21, G22
AM6254	VDDSHV5	G14	VDDSHV5	G21, G22
AM6254	VDDSHV6	H15	VDDSHV6	H21, H22
AM6254	VDDSHV6	H16	VDDSHV6	H21, H22
AM6254	VDDSHV_CANUART	G7	VDDSHV_CANUART	F11, G10
AM6254	VDDSHV_CANUART	H7	VDDSHV_CANUART	F11, G10
AM6254	VDDSHV_MCU	F10	VDDSHV_MCU	F12, G11
AM6254	VDDSHV_MCU	G10	VDDSHV_MCU	F12, G11
AM6254	VDDS_DDR	C1	VDDS_DDR	See Note (5)
AM6254	VDDS_DDR	J8	VDDS_DDR	See Note (5)
AM6254	VDDS_DDR	K7	VDDS_DDR	See Note (5)
AM6254	VDDS_DDR	K9	VDDS_DDR	See Note (5)
AM6254	VDDS_DDR	L8	VDDS_DDR	See Note (5)
AM6254	VDDS_DDR	U1	VDDS_DDR	See Note (5)
AM6254	VDDS_DDR_C	L7	VDDS_DDR	See Note (5)
AM6254	VDDS_OSC0	J7	VDDS_OSC0	D15
AM6254	VDD_CANUART	H8	VDD_CANUART	G12
AM6254	VDD_CORE	H12	VDD_CORE	See Note (3)
AM6254	VDD_CORE	H14	VDD_CORE	See Note (3)
AM6254	VDD_CORE	J11	VDD_CORE	See Note (3)
AM6254	VDD_CORE	J13	VDD_CORE	See Note (3)
AM6254	VDD_CORE	J9	VDD_CORE	See Note (3)
AM6254	VDD_CORE	K10	VDD_CORE	See Note (3)
AM6254	VDD_CORE	K14	VDD_CORE	See Note (3)
AM6254	VDD_CORE	L11	VDD_CORE	See Note (3)
AM6254	VDD_CORE	L13	VDD_CORE	See Note (3)
AM6254	VDD_CORE	M12	VDD_CORE	See Note (3)
AM6254	VDD_CORE	M14	VDD_CORE	See Note (3)
AM6254	VDD_CORE	M8	VDD_CORE	See Note (3)
AM6254	VDD_CORE	N11	VDD_CORE	See Note (3)
AM6254	VDD_CORE	N13	VDD_CORE	See Note (3)
AM6254	VDD_CORE	N9	VDD_CORE	See Note (3)
AM6254	VDD_CORE	P8	VDD_CORE	See Note (3)
AM6254	VMON_1P8_SOC	H9	VMON_1P8_SOC	C15
AM6254	VMON_3P3_SOC	K11	VMON_3P3_SOC	B15
AM6254	VMON_VSYS	F6	VMON_VSYS	A15
AM6254	VOUT0_DE	T17	VOUT0_DE	R25
AM6254	VOUT0_HSYNC	W21	VOUT0_HSYNC	P25
AM6254	VOUT0_PCLK	U17	VOUT0_PCLK	T26
AM6254	VOUT0_VSYNC	T16	VOUT0_VSYNC	R26
AM6254	VOUT0_DATA0	R21	VOUT0_DATA0	P26
AM6254	VOUT0_DATA1	P18	VOUT0_DATA1	N25
AM6254	VOUT0_DATA2	R18	VOUT0_DATA2	N26
AM6254	VOUT0_DATA3	R19	VOUT0_DATA3	M25
AM6254	VOUT0_DATA4	R20	VOUT0_DATA4	M26
AM6254	VOUT0_DATA5	T20	VOUT0_DATA5	U27
AM6254	VOUT0_DATA6	T21	VOUT0_DATA6	T27
AM6254	VOUT0_DATA7	T19	VOUT0_DATA7	T28
AM6254	VOUT0_DATA8	U21	VOUT0_DATA8	R27
AM6254	VOUT0_DATA9	R17	VOUT0_DATA9	R28
AM6254	VOUT0_DATA10	T18	VOUT0_DATA10	P27
AM6254	VOUT0_DATA11	U20	VOUT0_DATA11	P28
AM6254	VOUT0_DATA12	U19	VOUT0_DATA12	N27
AM6254	VOUT0_DATA13	V21	VOUT0_DATA13	N28
AM6254	VOUT0_DATA14	U18	VOUT0_DATA14	M27
AM6254	VOUT0_DATA15	V20	VOUT0_DATA15	M28
AM6254	VPP	F7	VPP	C16
AM6254	VSS	A1	VSS	See Note (1)
AM6254	VSS	A21	VSS	See Note (1)
AM6254	VSS	A4	VSS	See Note (1)
AM6254	VSS	AA1	VSS	See Note (1)
AM6254	VSS	AA12	VSS	See Note (1)
AM6254	VSS	AA15	VSS	See Note (1)
AM6254	VSS	AA21	VSS	See Note (1)
AM6254	VSS	AA9	VSS	See Note (1)
AM6254	VSS	D11	VSS	See Note (1)
AM6254	VSS	D19	VSS	See Note (1)
AM6254	VSS	D4	VSS	See Note (1)
AM6254	VSS	E2	VSS	See Note (1)
AM6254	VSS	F11	VSS	See Note (1)
AM6254	VSS	F13	VSS	See Note (1)
AM6254	VSS	F15	VSS	See Note (1)
AM6254	VSS	F4	VSS	See Note (1)
AM6254	VSS	F9	VSS	See Note (1)
AM6254	VSS	G16	VSS	See Note (1)
AM6254	VSS	G6	VSS	See Note (1)
AM6254	VSS	G9	VSS	See Note (1)
AM6254	VSS	H1	VSS	See Note (1)
AM6254	VSS	H13	VSS	See Note (1)
AM6254	VSS	H6	VSS	See Note (1)
AM6254	VSS	J10	VSS	See Note (1)
AM6254	VSS	J12	VSS	See Note (1)
AM6254	VSS	J14	VSS	See Note (1)
AM6254	VSS	J16	VSS	See Note (1)
AM6254	VSS	J6	VSS	See Note (1)
AM6254	VSS	K13	VSS	See Note (1)
AM6254	VSS	K3	VSS	See Note (1)
AM6254	VSS	K6	VSS	See Note (1)
AM6254	VSS	K8	VSS	See Note (1)
AM6254	VSS	L1	VSS	See Note (1)
AM6254	VSS	L10	VSS	See Note (1)
AM6254	VSS	L12	VSS	See Note (1)
AM6254	VSS	L14	VSS	See Note (1)
AM6254	VSS	L16	VSS	See Note (1)
AM6254	VSS	L6	VSS	See Note (1)
AM6254	VSS	M11	VSS	See Note (1)
AM6254	VSS	M16	VSS	See Note (1)
AM6254	VSS	M18	VSS	See Note (1)
AM6254	VSS	M6	VSS	See Note (1)
AM6254	VSS	M9	VSS	See Note (1)
AM6254	VSS	N12	VSS	See Note (1)
AM6254	VSS	N14	VSS	See Note (1)
AM6254	VSS	N6	VSS	See Note (1)
AM6254	VSS	P1	VSS	See Note (1)
AM6254	VSS	P10	VSS	See Note (1)
AM6254	VSS	P13	VSS	See Note (1)
AM6254	VSS	P15	VSS	See Note (1)
AM6254	VSS	P16	VSS	See Note (1)
AM6254	VSS	P3	VSS	See Note (1)
AM6254	VSS	P6	VSS	See Note (1)
AM6254	VSS	R16	VSS	See Note (1)
AM6254	VSS	R5	VSS	See Note (1)
AM6254	VSS	R7	VSS	See Note (1)
AM6254	VSS	R8	VSS	See Note (1)
AM6254	VSS	T10	VSS	See Note (1)
AM6254	VSS	T12	VSS	See Note (1)
AM6254	VSS	T15	VSS	See Note (1)
AM6254	VSS	T3	VSS	See Note (1)
AM6254	VSS	T6	VSS	See Note (1)
AM6254	VSS	T7	VSS	See Note (1)
AM6254	VSS	T9	VSS	See Note (1)
AM6254	VSS	U10	VSS	See Note (1)
AM6254	VSS	U13	VSS	See Note (1)
AM6254	VSS	U5	VSS	See Note (1)
AM6254	VSS	U8	VSS	See Note (1)
AM6254	VSS	V11	VSS	See Note (1)
AM6254	VSS	V14	VSS	See Note (1)
AM6254	VSS	V19	VSS	See Note (1)
AM6254	VSS	W10	VSS	See Note (1)
AM6254	VSS	W13	VSS	See Note (1)
AM6254	VSS	W7	VSS	See Note (1)
AM6254	VSS	Y11	VSS	See Note (1)
AM6254	VSS	Y14	VSS	See Note (1)
AM6254	VSS	Y3	VSS	See Note (1)
AM6254	VSS	Y4	VSS	See Note (1)
AM6254	VSS	Y6	VSS	See Note (1)
AM6254	WKUP_CLKOUT0	B12	WKUP_CLKOUT0	C7
AM6254	WKUP_I2C0_SCL	E9	WKUP_I2C0_SCL	A8
AM6254	WKUP_I2C0_SDA	A9	WKUP_I2C0_SDA	B8
AM6254	WKUP_LFOSC0_XI	A2	WKUP_LFOSC0_XI	H1
AM6254	WKUP_LFOSC0_XO	A3	WKUP_LFOSC0_XO	H2
AM6254	WKUP_UART0_CTSn	A7	WKUP_UART0_CTSN	D1
AM6254	WKUP_UART0_RTSn	B4	WKUP_UART0_RTSN	D2
AM6254	WKUP_UART0_RXD	B5	WKUP_UART0_RXD	C2
AM6254	WKUP_UART0_TXD	C6	WKUP_UART0_TXD	C1

Notes:

(1)	See VSS pin in OSD62x-PM Datasheet	A2, A14, A27, B1, B14, B28, C3, C4, C14, D3, D4, D14, E3, E4, E5, E6, E7, E8, E9, E10, E11, E12, E13, E16, E17, E18, E19, E20, E21, E22, E23, E24, F19, F20, F21, F22, F23, F24, G19, G20, G23, G24, H19, H20, H24, J14, J15, J19, J20, J24, K6, K7, K8, K9, K14, K15, K19, K20, K24, L5, L6, L7, L8, L19, L20, L24, M4, M5, M6, M7, M20, M23, M24, N3, N4, N5, N6, N20, N21, N22, N23, N24, P3, P4, P5, P16, P17, P18, P19, P20, P21, P22, P23, P24, R3, R4, T3, T19, U1, U19, U28, V2, V19, V27
(2)	See NC pin in OSD62x-PM Datasheet	E14, E15, F3, F15, F16, F17, F18, G3, G4, G5, G6, G7, G8, G9, G17, G18, H3, H4, H5, H6, H7, H8, H9, H10, H11, H23, J2, J3, J4 J5, J6, J7, J8, J9, J10, J11, J23, K3, K4, K5, K23, L3, L4, L12, L16, L23, M3, M11, M14, M15, M16, M17, M19, N15, N16, N19, P6, P7, P8, P9, P14, P15, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, U18, V18
(3)	See VDD_CORE pin in OSD62x-PM Datasheet	G13, G14, G15, G16, H12, H13, H14, H15, H16, J12, J13, J16, K12, K13, K16, L13, L14, L15
(4)	See VDDR_CORE pin in OSD62x-PM Datasheet	H17, H18, J17, J18, K17, K18, L17, L18
(5)	See VDDS_DDR pin in OSD62x-PM Datasheet	K10, K11, L9, L10, L11, M8, M9, M10, N8, N9

Revision History

Revision Number	Revision Date	Changes	Author
1	06/05/2025	Initial Revision	Erik Welsh
1.1	06/26/2025	Updated VMON_SYS to VMON_VSYS	Erik Welsh

Notice

The information provided within this document is for informational use only. Octavo Systems provides no guarantees or warranty to the information contained.

Pin Mapping Between OSD62x-PM and the AM62x

OSD62x-PM to AM6254 Pin Mapping

Notes:

AM6254 to OSD62x-PM Pin Mapping

Notes:

Revision History

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Pin Mapping Between OSD62x-PM and the AM62x

OSD62x-PM to AM6254 Pin Mapping

Notes:

AM6254 to OSD62x-PM Pin Mapping

Notes:

Revision History

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