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OSD62x-PM Schematic Checklist

Published On: July, 23, 2025 By: Greg Sheridan

 

This application note provides a checklist of items to review for custom designs using OSD62x-PM. It is recommended to go through and check each item in this schematic checklist to make sure all specifications are followed for AM62x SoC and OSD62x-PM device.

 

NOTE: While this checklist covers a lot of design specifications for AM62x SoC, it is not exhaustive for all peripherals. Please refer to the Technical Reference Manual and other TI documentation for exhaustive information on all peripherals.

Table of Contents

1.

OSD62x-PM Power

Topic NumberOSD62x-PMChecklist Topic
62_POWER_1✓All power rail inputs to OSD62x-PM must follow the recommended operating conditions outlined in Table 7-3 and Table 7-4 of OSD62x-PM Datasheet (https://octavosystems.com/docs/osd62-pm-datasheet/). Voltage must not drop below MIN or rise above MAX voltage specified for any amount of time during normal operation.
62_POWER_2✓OSD62x-PM has power sequencing requirements. Review power up and power down sequencing requirements for OSD62x-PM device in Section 2.1.2 of OSD62x-PM Power Application Note and make sure that the power system does not violate sequencing requirements.
62_POWER_3✓If TPS65219 PMIC is used, all power rails must be discharged below 300mV (PMIC specs: VBUCKx_SCG_TH/VLODx_SCG_TH) before initiating a power-up sequence. This also applies to anytime a power rail drops below the minimum value defined in Recommended Operating Conditions.

The TPS65219 PMIC executes two residual voltage checks; the first one occurs before the power-up sequence is executed and a second occurs during the power-up sequence (right before each rail is turned ON). If the back feeding issue on any rail exist before the PMIC executes the power-up sequence, then none of the rails will turn-ON.

Review the power system to make sure there is no condition that puts a residual voltage on PMIC power rails when the rails are turned OFF.
62_POWER_4✓The AM62x processor includes multiple analog supply pins that provide power to sensitive analog circuitry. VDDA_MCU, VDDS_OSC0, VDDA_PLL0, VDDA_PLL1, VDDA_PLL2, VDDA_1P8_CSIRX0, VDDA_1P8_OLDI0, VDDA_1P8_USB, and VDDA_TEMP are 1.8V analog supplies. VDDA_3P3_USB is a 3.3V analog supply. These power inputs may require noise filtering between the output of the regulator and the input of the OSD62x-PM based on the noise in the power system and the distance between the respective regulator and the power input. Optimized filtered power supplies recommended are shown in this reference design: https://www.ti.com/tool/SK-AM62-LP

Grouping of filtered rails in the reference design is as follows:

GROUP 1 – VDDA_1P8_OLDI, VDDA_1P8_CSIRX0

GROUP 2 – VDDS_OSC0

GROUP 3 – VDDA_TEMP, VDDA_PLL1, VDDA_PLL2, VDDA_PLL3, VDDA_MCU

GROUP 4 – VDDA_1P8_USB

GROUP 5 – VDDA_3P3_USB

NOTE: OSD62-PM-BRK does not implement this recommended filtration. Implementation is based on noise in the power system and distance between regulators and OSD62x-PM power rails.
62_POWER_5✓If it is necessary to perform OTP programming, a GPIO activated LDO with 400mA current capacity is recommended for powering VPP voltage rail. VPP rail must not be active when OTP programming is not in progress. A 2.2uF (at output of LDO) and 0.1uF (close to OSD62x-PM VPP input) are recommended.

Given the transient current requirements during OTP programming, using a load switch/FET is not recommended.

Leave VPP pin unconnected if OTP programming is not necessary.
62_POWER_6✓AM62x SoC has power rail slew rate requirement. All power rails must have a slew rate of < 18mV/us. For reference, a 1.8V rail should take >100us to come up.
62_POWER_7✓If Partial IO low power mode is used, VDD_CANUART (0.75V) and VDDSHV_CANUART (1.8V/3.3V) must be supplied through always-ON power supplies. Review power sequencing (62_POWER_2) to understand changes to the power sequencing when Partial IO low power mode is supported.

VDD_CORE must always be < VDD_CANUART + 0.18V. This requires VDD_CANUART to ramp up before VDD_CORE and ramp down after VDD_CORE if Partial IO power mode is supported.
62_POWER_8✓The potential applied to VDDR_CORE must never exceed the potential applied to VDD_CORE +0.18V during power-up or power-down.

The sequencing requires VDD_CORE to ramp up before VDDR_CORE and ramp down after VDDR_CORE when VDD_CORE is operating at 0.75V. VDD_CORE and VDDR_CORE can be ramped together when VDD_CORE is set to 0.85V.
62_POWER_9✓All power inputs to OSD62x-PM must be supplied by power rails that have sufficient current capacity to supply the grouping of power rails implemented for application requirements. Review OSD62x-PM Power Application Note ([LINK]) for budgeting analysis of custom designs.
62_POWER_10✓AM62x SoC does not support dynamic voltage scaling on VDD_CORE voltage rail. Voltage input to this rail must be chosen as per A53 core operating frequency:

1.4 GHz - 0.85V

1.2 GHz - 0.75V
2.

OSD62x-PM Configuration

Topic NumberOSD62x-PMChecklist Topic
62_CONFIG_1✓MCU_ERRORn must be connected to VSS through a separate external pull resistor if there are PCB traces attached to OSD62x-PM ball. This is needed to hold the pin to a logic LOW level.

If no PCB trace is connected to this ball, no pull-down is needed, and the internal pull-down can be used to hold this pin LOW.
62_CONFIG_2✓MCU_ERRORn is an active LOW pin indicating the MCU domain Error Signaling Module (ESM) status. This signal can be used to inform an external device that the MCU ran into an error that needs to be addressed.

MCU_ERRORn is LOW during POR. It is not affected by Warm RESET. The pin logic is only reset by asserting MCU_PORz LOW.

MCU_ERRORn belongs to VDDS_OSC0 IO domain.
62_CONFIG_3✓TRSTn must be connected to VSS through a separate external pull resistor if there are PCB traces attached to OSD62x-PM ball. This is needed to hold the pin to a logic LOW level.

If no PCB trace is connected to this ball, no pull-down is needed, and the internal pull-down can be used to hold this pin LOW.
62_CONFIG_4✓EMU0, EMU1, MCU_RESETz, TCK, TDI, TMS must be pulled up to VDDSHV_MCU (IO domain voltage) if these pins are used on board. This is needed to hold these pins to a logic HIGH level. Use 10K or 47K.

If no PCB traces are connected to these pins, no external pull-up is needed, and internal pull-ups can be used to hold these pins HIGH.
62_CONFIG_5✓MCU_I2C0_SCL, MCU_I2C0_SDA, WKUP_I2C0_SCL, WKUP_I2C0_SDA must be connected to VDDSHV_MCU (IO domain voltage) through separate pull-up resistors to ensure the inputs associated with these balls are held to a valid logic HIGH level. Depending on use, an appropriate resistor value should be chosen for the I2C bus. If unused, a 10K or 47K resistor is sufficient.
62_CONFIG_6✓The VMON_VSYS pin provides a way to monitor a system power supply. The system power supply needs to be connected to VMON_VSYS via a resistor divider to VSS. VMON_VSYS input threshold value is 0.45V ± 3%. 1% resistors with similar temperature coefficients are recommended. Input leakage current on this pin can be 2.5uA to 10uA. The following figure shows recommended circuit for 5V input with trigger threshold of 4.5 V.


Diagram


C1 is 22pF in an example circuit.

See Section “System Power Supply Monitor Design Guidelines” in AM625 Datasheet for more information.

If you do not need precise monitoring, you can just use a resistor divider that follows the above voltage recommendations, such as the implementation on the OSD62-PM-BRK or the BeaglePlay.
62_CONFIG_7✓If VMON_VSYS is not used, this ball must be connected directly to VSS.
62_CONFIG_8✓If VMON_1P8_SOC and VMON_3P3_SOC are not used to monitor the SOC power rails, these balls must still be connected to their respective 1.8V and 3.3V power rails.
62_CONFIG_9✓PMIC_LPM_EN0 is an output of the AM62x SoC to signal the power system to enable Low Power Mode (Active LOW) or Normal Mode operation (Active HIGH).

PMIC_LPM_EN0 belongs to VDDSHV_CANUART IO domain.

The PMIC_LPM_EN0 pin requires an external pullup to the VDDSHV_CANUART power source. The pin status is HiZ during reset, which allows the pullup to turn on the PMIC as soon as the always on VDDSHV_CANUART supply ramps up. The pin is driven high once the device is released from reset (rising edge of MCU_PORz input).

For example, in OSD62-PM-BRK, PMIC_LPM_EN0 is connected to MODE/STBY pin of TPS6521903 to signal the PMIC to enter Auto-PFM, low power operation. It is pulled up to VIN-3P3-LS rail, which powers VDDSHV_CANUART.
3.

OSD62x-PM Reset

Topic NumberOSD62x-PMChecklist Topic
62_RESET_1✓MCU_PORz must be used to cold reset the AM62x SoC inside the OSD62x-PM. This reset input resets all cores, IOs and registers present on the device.

This reset must be released only after all power rails are up and stable. MCU_PORz release delay after all the power supplies ramp must be > 9.5ms.

MCU_PORz belongs to VDDS_OSC0 (1.8V) IO domain.

Leaving MCU_PORz unconnected is not allowed.
62_RESET_2✓The rise/fall time for the reset signal (MCU_PORz) must be less than 1000ns. It is recommended to make sure the slew rate for the IO that is driving this pin is much better than this specification. A discrete push pull output buffer is recommended to minimize the slew. A 22pF glitch filter is recommended at the input of MCU_PORz

Rise of MCU_PORz must be monotonic with no glitches.
62_RESET_3✓MCU_RESETz can be used as a WARM Reset input to the device. It is an active LOW input resetting the MCU and MAIN domains except selected CTRLMMR_RST_CTRL and CTRLMMR_MCU_RST_CTRL register bits. These bits are only reset by PORz. IOs for the MCU and MAIN domain are not affected by this input.

MCU_RESETz belongs to VDDSHV_MCU IO domain.
62_RESET_4✓MCU_RESETz must be pulled up to VDDSHV_MCU (IO domain voltage) if this pin is used on the board. This is needed to hold this pin to a logic HIGH level. Use 10K or 47K.

If no PCB trace is connected to this ball, no pull-up is needed, and the internal pull-up can be used to hold this pin HIGH.
62_RESET_5✓RESET_REQz can be used to request a reset to the MAIN domain, while optionally isolating the MCU domain. IOs of the MAIN and MCU domains are not affected. All processor cores (A53, SMS, R5F) are reset.

Minimum time required for RESET_REQz to be asserted LOW to generate a reset request is 1200ns.

RESET_REQz belongs to VDDSHV0 IO domain.
62_RESET_6✓RESET_REQz must be pulled up to VDDSHV0 (IO domain voltage) if this pin is used on the board. This is needed to hold this pin to a logic HIGH level. Use 10K or 47K.

If no PCB trace is connected to this ball, no pull-up is needed, and the internal pull-up can be used to hold this pin HIGH.
62_RESET_7✓RESETSTATz pin indicates the MAIN domain internal reset status (active LOW). This pin can be used to reset other devices on board when the MAIN domain is in RESET.

RESETSTATz belongs to VDDSHV0 IO domain.
62_RESET_8✓MCU_RESETSTATz pin indicates warm reset status of the MCU domain. MCU_RESETSTATz belongs to VDDSHV_MCU IO domain.

Due to erratum i2407 (AM625 Errata: https://www.ti.com/lit/er/sprz487f/sprz487f.pdf), do not use MCU_RESETSTATz to reset other devices. However, MCU_RESETSTATz can still be used for debug.
62_RESET_9✓PORz_OUT pin indicates the status of the MAIN domain power-on-reset. This pin can be used to perform actions based on POR status of the device.

PORz_OUT belongs to VDDSHV0 IO domain.
62_RESET_10✓When not used, RESET status pins (RESETSTATz, MCU_RESETSTATz and PORz_OUT) can be left unconnected.
62_RESET_11✓When RESET status outputs are used to RESET other devices on the board, the IO level must match the IO level of the RESET input of the device.

If IO levels of intended RESET status output and RESET input of the device are different, a level translation must be performed via open drain buffer or level shifter chip.

See for example eMMC RESET mechanism in AM62x EVM (proc142a):


Block diagram
62_RESET_11✓RESET status outputs of AM62x SoC have timing delays associated with them. They must be considered when designing reset mechanisms to other devices on the board.

Refer to Section “Reset Timing” in AM625 Datasheet for specifications.
4.

OSD62x-PM Clock

Topic NumberOSD62x-PMChecklist Topic
62_CLOCK_1✓MCU_OSC0_XI/MCU_OSC0_XO are main oscillator inputs for AM62x SoC interface MCU_OSC0. The crystal/oscillator for this input must be 25MHz.

If RGMII/RMII interface is used in the application with clock derived from this clock input, the frequency stability and tolerance specification must be ±50ppm. If RGMII/RMII is not used, ±100ppm crystal/oscillator can be used.

Other crystal specifications can be found in Table “MCU_OSC0 Crystal Circuit Requirements” of AM625 Datasheet.


Diagram


The above circuit shows the crystal-based circuit on MCU_OSC0 interface with all capacitances defined. The values of CL1 and CL2 can be determined by the following equations.

CL1 = (2CL) - (CPCBXI + CXI)

CL2 = (2CL) - (CPCBXO + CXO)

Where CL is the Load Capacitance specified by crystal manufacturer.

Cshunt specification is also listed in Table “MCU_OSC0 Crystal Circuit Requirements” of AM625 Datasheet:


Diagram


CO + CPCBXIXO + CXIXO ? Cshunt

Place all components associated with is clock input as close to OSD62x-PM as possible.
62_CLOCK_2✓An LVCMOS Oscillator can be used instead of a crystal to generate 25MHz on MCU_OSC0_XI pin. MCU_OSC0_XO pin must be connected to VSS when an oscillator is used. The following is the circuit:


Diagram


The power rail used to power the oscillator must be the same power rail powering VDDS_OSC0.

A DC steady-state condition is not allowed on MCU_OSC0_XI when the oscillator is powered up
62_CLOCK_3✓WKUP_LFOSC0_XI/WKUP_LFOSC0_XO are wake-up oscillator input pins for WKUP_LFOSC0. The crystal/oscillator for this input needs to be 32.768KHz.

This input is optional as 32KHz can be generated internal to AM62x SoC. The internally generated clock source is not as accurate. The need for this external input is based on accuracy requirements for this clock source. Please review AM62x Clock Tree tool to understand the usage of WKUP_LFOSC0 (https://www.ti.com/tool/CLOCKTREETOOL).

The recommended circuit for a crystal based LFOSC0 circuit is shown below:


Diagram


In the above circuit Cf1 and Cf2 must be chosen such that the following equation is satisfied:

CL=Cf1Cf2/(Cf1+Cf2)

Where CL is the load capacitance of the crystal used.

Additional specifications for this circuit are shown in Table “WKUP_LFOSC0 Crystal Electrical Characteristics” of AM625 Datsheet.

Crystal has a minimum load capacitance of 6 pF and a maximum value of 12 pF.

Place all components associated with is clock input as close to OSD62x-PM as possible.
62_CLOCK_4✓An LVCMOS Oscillator can be used instead of a crystal to generate 32.768KHz on WKUP_LFOSC0_XI pin. WKUP_LFOSC0_XO pin must be connected to VSS when an oscillator is used. The following is the circuit:


Diagram


The power rail used to power the oscillator must be the same power rail powering VDDS_OSC0.
62_CLOCK_5✓When WKUP_LFOSC0 clock input is not used, the following circuit is recommended:


Diagram


- WKUP_LFOSC0_XI – GND

- WKUP_LFOSC0_XO – NC
62_CLOCK_6✓Some clock outputs of AM62x SOC can only be used for test/debug purposes. They are listed below:

MCU_SYSCLKOUT0, MCU_OBSCLK0, SYSCLKOUT0, OBSCLK0
62_CLOCK_7✓CLKOUT0 is the Ethernet subsystem clock (MAIN_PLL2_HSDIV1_CLKOUT) divided-by-5 or divided-by-10. This clock output was provided as an optional source to the external PHY. When configured to operate as the RMII Clock source (50 MHz) the signal must also be routed back to the respective

RMII[x]_REF_CLK pin for proper device operation.

CLKOUT0 can be used as clock source for external devices.
62_CLOCK_8✓WKUP_CLKOUT0 is a buffered output of the high frequency oscillator (HFOSC0) available after reset and can be used as clock source for external devices.
5.

OSD62x-PM I2C

Topic NumberOSD62x-PMChecklist Topic
62_I2C_1✓MCU_12C0 and WKUP_I2C0 interfaces have open-drain IOs. Add 4.7K pull-ups to VDSHV_MCU. The rise and fall times of the I2C signals connected to these ports must not exceed a slew rate of 0.08 V/ns (or 8E+7 V/s). This limit is more restrictive than the minimum fall time limits defined in the I2C specification. Therefore, it may be necessary to add additional capacitance to the I2C signals to slow the rise and fall times such that they do not exceed a slew rate of 0.08 V/ns.
62_I2C_2✓I2C HS mode (3.4 Mbps) is not supported when operating the IO in 3.3 V mode.
62_I2C_3✓I2C0, I2C1, I2C2 and I2C3 use LVCMOS IO buffers. Pull-ups are recommended when used. To calculate pull-up value on I2C interface refer to this app note: https://www.ti.com/lit/an/slva689/slva689.pdf.

Pull-ups to I2C interfaces must be to the same power rail that powers the corresponding VDDSHV domain.

These I2C interfaces only support 100Kbps Standard mode and 400Kbps Fast-mode. Because they are implemented with LVCMOS IOs, they have a faster fall time than specified in I2C specification.
62_I2C_4✓When implementing the recommended PMIC (TPS65219), the reference SDK assumes I2C connection on I2C0 interface.
6.

OSD62x-PM UART

Topic NumberOSD62x-PMChecklist Topic
62_UART_1✓The following debug UART channels are used for various purposes:

MAIN_UART0 – Used for Linux and U-Boot on A53

MAIN_UART1 – TIFS output

WKUP_UART0 – DM Firmware output

MCU_UART0 – MCU+SDK console

The board must be provisioned to access these peripherals if debug access is required.
62_UART_2✓A pullup is recommended on the processor UART receive inputs (UARTn_RXD (n = 0-6), MCU_UART0_RXD, and WKUP_UART0_RXD) to avoid floating RX input coupling with board noise.
62_UART_3✓Make sure null-modem connection is implemented for UART connections: RX (AM62x UART input) to TX (Device output) and TX (AM62x UART output) to RX (Device input).
7.

OSD62x-PM Boot Configuration

Topic NumberOSD62x-PMChecklist Topic
62_BOOT_1✓Boot mode configuration for processor is latched at the rising edge of PORz_OUT.

Boot mode pins are GPMC0_AD[0-15]. These pins must be connected to either VDDSHV3 or VSS via separate pull resistors to ensure the inputs associated with these balls are held to a valid logic high or low level as appropriate to select the desired device boot mode. Leaving any of the boot mode inputs unconnected is not recommended or allowed.

Shorting the boot mode pins directly to VSS is not recommended.
62_BOOT_2✓1514131211109876543210
ResResBackup

Boot

config		Backup boot modePrimary boot mode configPrimary Boot modePLL config

(MCU_OSC0)
The above mapping provides configuration for ROM code regarding boot mode.

PLL configuration must be set to 25MHz as follows for AM625 SoC.
210Configuration
01125MHz

Primary boot mode configuration is as follows:
B9B8B7B6B5B4B3Mode
resmodecsel0011SPI
clkout0link Info0100RGMII
clkoutclk src00101RMII
bus rstresaddr0110I2C
resresres0111UART
portresFS/raw1000MMCSD
resresres1001eMMC
core voltagemodelane swap1010USB
resresres1011NAND
resresres1100NOR
SFPDread cmdmode1110xSPI
resARM/

thumb		No/dev1111No boot

Backup boot configuration is as follows:
B13B12B11B10Mode
res000None
mode001USB
res011UART
IF100Ethernet
port101SD/eMMC
res110SPI
res111I2C
Refer to the reference manual “Boot Modes” section for more information on the primary and backup boot config pins
62_BOOT_3✓Make sure the pull-up/pull-down resistors that are setting the bootmode during reset are not over-ridden with a connected peripheral. If there is a concern, add buffers (SN74AVC8T245) enabled by RESETSTARTz signal to isolate the boot mode configuration from the rest of the alternate usage of the boot mode pins.

Here is an example of this configuration:




BOOTMODEON (Enable input of the buffers) signal configuration:






When buffers are used for boot mode setting, use 1K series resistors between output of buffers to boot mode configuration pins. These resistors isolate the boot mode control logic after the value is latched.
62_BOOT_4✓When dip switches are used for boot configuration, use a resistor divider ratio of 470? (pullup) and 47k? (pulldown) for improved noise performance
62_BOOT_5✓When the boot mode is configured using only resistors, a standard resistor (same value for pullup and pulldown) such as 10K can be used.
62_BOOT_6✓When using an Ethernet boot and a Reduced Gigabit Media Independent Interface (RGMII), implement an EPHY into the design that starts RGMII_ID mode on the EPHY RX data path and disables RGMII_ID mode on the TX data path (the processor implements RGMII_ID on the TX outputs). Processor ROM does not enable or disable RGMII_ID mode on attached EPHYs programmatically. Typically, RGMII_ID setting is accomplished via pin strapping on the EPHY.

Refer to Erratum i2329 (AM625 Errata: https://www.ti.com/lit/er/sprz487f/sprz487f.pdf) when implementing Ethernet boot
62_BOOT_7✓USB0 Can be used for boot. However, there is an erratum associated with this use case. Please see i2328 in AM625 Errata: https://www.ti.com/lit/er/sprz487f/sprz487f.pdf.

If your project will use USB MSC boot in final products, and you don't have control on which USB MSC device will be used, it is not recommended to use USB MSC boot.
8.

OSD62x-PM USB

Topic NumberOSD62x-PMChecklist Topic
62_USB_1✓If USB0 and USB1 interfaces are not used, VDDA_CORE_USB, VDDA_1P8_USB, and VDDA_3P3_USB can be connected to VSS.
62_USB_2✓If either USB0 or USB1 is used, VDDA_CORE_USB, VDDA_1P8_USB and VDDA_3P3_USB must be connected to valid power rails according to the specifications listed in the Datasheet.
62_USB_3✓If USB0 or USB1 interfaces are not used, leave DP, DM and VBUS pins unconnected.
62_USB_4✓USB0_VBUS and USB1_VBUS pins (3.4V Max): An external resistor divider is required to limit the voltage applied to this device pin. USB0_VBUS pin can be considered fail-safe because of the following circuit (It can have external voltage when SoC is in RESET):


Diagram


The above circuit allows VBUS to go up to 30V. Zener can be removed if VBUS is never > 5.5V. In this case, 16.5K and 3.5K resistors can be replaced with a single 20K resistor.

Connecting a permanent supply is not recommended (equivalent to the divider value) to the USB0_VBUS pin since connection of supply without resistor divider violates fail-safe operation.
62_USB_5✓VBUS connection for Host interface is optional. It is recommended to connect the VBUS when the USB interface is configured as Device.
62_USB_6✓When USB interface is used as HOST, USBx_DRVVBUS can be used to control the power (load) switch. The USB interface or the Linux driver is not checking the status of VBUS to determine if there is a fault condition. In that case, you should connect the fault output of the VBUS power (load) switch to a GPIO and configure the GPIO to generate an interrupt that indicates there has been an over-current condition. USBx_DRVVBUS has an internal pulldown enabled by default.
62_USB_7✓USBx_DP and USBx_DM should never have any series resistors or capacitance on these signals. These signals should be straight traces to the connector with no stubs or test points. It is recommended to maintain a 90-ohm differential transmission line to prevent any reflections.

Common-mode chokes may be needed for EMI/EMC control on USB DM/DP signals. Note that these may reduce the signal amplitude and degrade performance
62_USB_8✓Ensure the recommended capacitors are provided for the VBUS supply near to the connector (For Host > 120 uF and Device (1-10 uF))
62_USB_9✓USB0 supports USB DFU boot mode. Device port on USB0 must be implemented to enable flashing/firmware update via USB.
62_USB_10✓For dual role operation: If the custom board design uses USB Micro-AB connector, the USBn_ID signal from the connector can be routed

to the processor GPIO pin. USBn_ID can be connected to any available GPIO pin. The GPIO pin is specified in the board device tree file, including the pinmux setting of the GPIO pin.

ID pin connection corresponding to USB port role is given below:

Pulled to GND – Host mode

Floating/pulled High – Peripheral mode
62_USB_11✓If USB port is connected to type-c connector, a USB-C controller is needed to implement dual role operation. See https://www.ti.com/tool/SK-AM62B-P1#design-files for reference implementation.
62_USB_12✓For USB-C device operation without a USB-C controller device, 5.1K pull-down on CC pins are needed. Short both side of DM and DP connector pins of USBC port.
9.

OSD62x-PM CSI

Topic NumberOSD62x-PMChecklist Topic
62_CSI_1✓If CSIRX0 interface is not used and boundary scan function is not needed, VDDA_CORE_CSIRX0 and VDDA_1P8_CSIRX0 can be connected to VSS.
62_CSI_2✓If CSIRX0 interface is used or boundary scan function is needed, VDDA_CORE_CSIRX0 and VDDA_1P8_CSIRX0 must be connected to valid power rails according to the specifications listed in the Datasheet.
62_CSI_3✓If CSIRX0 interface is not used, CSI0_RXCLKN, CSI0_RXCLKP, CSI0_RXN0, CSI0_RXP0, CSI0_RXN1, CSI0_RXP1, CSI0_RXN2, CSI0_RXP2, CSI0_RXN3 and CSI0_RXP3 must be left unconnected.
62_CSI_4✓When used, clock and data lanes of CSIRX0 must be routed as differential pairs with 100Ohm differential impedance.
62_CSI_5✓Swapping the lanes and polarity within each lane is possible, but software modifications are necessary.

See https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1263174/sk-am62a-lp-csi-2-d-phy-clock-and-data-lane-polarity-inversion-swap for details.
10.

OSD62x-PM OLDI

Topic NumberOSD62x-PMChecklist Topic
62_OLDI_1✓If OLDI interface is not used, OLDI0_A0N, OLDI0_A0P, OLDI0_A1N, OLDI0_A1P, OLDI0_A2N, OLDI0_A2P, OLDI0_A3N, OLDI0_A3P, OLDI0_A4N, OLDI0_A4P, OLDI0_A5N, OLDI0_A5P, OLDI0_A6N, OLDI0_A6P, OLDI0_A7N, OLDI0_A7P, OLDI0_CLK0N, OLDI0_CLK0P, OLDI0_CLK1N and OLDI0_CLK1P must be left unconnected
62_OLDI_2✓When used, data and clock lanes of OLDI interface must be routed as differential pairs with 100Ohm differential impedance.
62_OLDI_3✓AM62x SoC OLDI interface supports 1 X 8 lane (dual link mode) and 2 X 4 lane (single link). In dual mode LCD configuration, A0 through A3 correspond to the ODD pixels and A4 through A7 correspond to the even pixels.
62_OLDI_4✓It is possible to connect two displays and use the OLDI in single link mode. However, due to HW limitations, both displays will be mirrored. OLDI cannot do 2 streams.
62_OLDI_5✓You can use RESETSTATz for reset on screen. Make sure to match IO level of the screen used to the reset origin.
11.

OSD62x-PM eMMC

Topic NumberOSD62x-PMChecklist Topic
62_EMMC_1✓MMC0 interface is the only MMC interface on AM62x SoC that is 8 bit wide. 8 bit eMMC interface must use MMC0 interface.

MMC0 does not have MMC_SD and MMC_WP for SD card implementation. However, MMC0 can be used for SDIO interfacing.
62_EMMC_2?eMMC boot is only available on MMC0 interface.

Addition Boot mode pin configuration needed for eMMC boot:
Boot mode pin 9Boot mode pin 7Mode
00MMC0 Filesystem mode
01MMC0 Raw mode
62_EMMC_3✓MMC0 interface belongs to VDDSHV4 IO domain. It is recommended to use the same 3.3V/1.8V power rail to power VDDSHV4 and VCCQ input of the eMMC.
62_EMMC_4✓If HS200 is targeted for eMMC, 1.8V signaling must be implemented on MMC interface.
62_EMMC_5✓It is recommended to add a pull-down on MMC_CLK signal to hold the signal LOW when AM62x IO buffers are not active.
62_EMMC_6✓Make sure decoupling caps are added to VCC and VCCQ. Recommended ones are 1x2.2uF, 2x0.1uF.
62_EMMC_7✓A series resistor footprint is recommended on MMC_CLK line close to OSD62x-PM device. A 22 Ohm resistor may be necessary to improve signal integrity.
62_EMMC_8✓Pull-ups need to be implemented to corresponding SHV rail of the MMC bank being used. CMD and D0 pull-ups are necessary. For D1-D7, internal pull-ups can be configured in bootloader.
62_EMMC_9✓Either an AND logic gate with RESETSTATz and IO output (pulled up) or RESETSTATz alone can be used to reset eMMC. Make sure that IO voltage level for the device is matched with RESETSTATz. If not, a buffer is recommended.

An example of buffer circuit implementation is shown below:


Diagram
12.

OSD62x-PM SD

Topic NumberOSD62x-PMChecklist Topic
62_SD_1✓MMC1 and MMC2 interfaces can be used to interface with SD cards. SD card boot is only available on MMC1 interface.

Addition boot mode pin configuration needed for SD boot mode on MMC1:
Boot mode pin 9Boot mode pin 7Mode
10MMC1 File system mode
11MMC1 Raw mode
62_SD_2✓MMC1 interface SDCD (card detect) pin must be connected to a mechanism that pulls it LOW when an SD card is inserted. ROM code checks for an active LOW SDCD signal to detect presence of an SD card. SD card holders normally have a pin that can signal insertion of an SD card. This signal should be active LOW polarity.

If an SD card holder that has an active HIGH SD card insertion indicator pin, the signal needs to be inverted when connecting to MMC interface SDCD input pin. OSD62-PM-BRK shows this configuration:


Diagram
62_SD_3✓VDDSHV5 (MMC1) and VDDSHV6 (MMC2) IO domains support 1.8V and 3.3V dynamic voltage switching, allowing operating voltage of SD to change from 3.3V to 1.8V on the go.

To support UHS-1 SD card speeds, dynamic controlled switching from 3.3V to 1.8V signaling is required for VDDSHV5 (MMC1) and VDDSHV6 (MMC0). So, a power supply that can dynamically switch between 3.3V and 1.8V needs to be connected to the IO domain supply input corresponding to UHS-1 supported SD card interface.
62_SD_4✓VDDSHV5 (MMC1) and VDDSHV6 (MMC2) supplies are required to start with 3.3V signaling and allow changing to 1.8V triggered by software for MMC use case.
62_SD_5✓SD card’s VDD input needs to be powered using a fixed 3.3V supply.

For UHS-1 mode supported SD sockets, the 3.3V supply powering VDD input of the SD card needs to be controlled through AM62x IO to allow the SoC to cycle SD card power. For this purpose, a power switch is recommended. The following example implementation shows OSD62-PM-BRK’s VDD_SD configuration:


Diagram


This is required because cycling power is the only way to get the SD card out of 1.8V IO mode back to 3.3V IO mode.
62_SD_6✓ROM code does not interact with WP (Write Protect) pin of MMC interface for boot. WP pin polarity if used:

0 (Logic Low - VSS) = Write Protection Disabled (Write Enabled)

1 (Logic High - VDD) = Write Protection Enabled (Write Disabled)
62_SD_7✓MMCx_SDCD and MMCx_WP pins belong to VDDSHV0 IO domain.

NOTE: The IO domain for these pins is different from IO domains of MMC1 and MMC2.
62_SD_8✓Pull-ups must be implemented on CMD and DAT0 – DAT3 as per SD specification. 10K pull-ups are good for noise immunity.

Resistors are recommended to be connected to the same voltage rail that powers corresponding MMC interface IO domain inputs (MMC1 – VDDSHV5. MMC2 – VDDSHV6). This is critical when the interface supports UHS-1 speeds with dynamic voltage switching.
62_SD_9✓A series resistor footprint is recommended on MMC_CLK line close to OSD62x-PM device. A 22 Ohm resistor may be necessary to improve signal integrity.

NOTE: This is not implemented on OSD62-PM-BRK as SD card socket is places close to OSD62x-PM device reducing noise integrity concerns.
62_SD_10✓It is recommended to add a pull-down on MMC_CLK signal to hold the signal LOW when AM62x IO buffers are not active.
13.

OSD62x-PM DPI

Topic NumberOSD62x-PMChecklist Topic
62_DPI_1✓Interface support includes 12-, 16-, 18-, and 24-bit RGB active matrix displays. When connecting only 16-bit data to an 18-bit panel (BGR565 to BGR666), connect D0-D4 to B1-B5 on LCD, D5-D10 to G0-G5 on the LCD, and D11-D15 to R1-R5 on LCD. On the 18-bit panel, connect B0 to B5 and R0 to R5.
62_DPI_2✓Add provisional 0Ohm on VOUT0_PCLK close to processor output pin to be able to adjust it for signal integrity during bring-up.
62_DPI_3✓The processor DPI interface is powered by VDDSHV3 supply rail. Make sure all pull-up/pull-down resistors are to the power rail powering VDDSHV3.
62_DPI_4✓You can use RESETSTATz for reset on screen. Make sure to match IO level of the screen used to the reset origin.
14.

OSD62x-PM OSPI

Topic NumberOSD62x-PMChecklist Topic
62_OSPI_1✓OSPI interface belongs to VDDSHV1 IO domain. It is recommended to connect VDDSHV1 and the IO supply rail of the attached device to the same supply source.
62_OSPI_2✓Pull-ups are recommended for DQx signals.
62_OSPI_3✓It is recommended to add a pull-down on OSPI0_CLK signal to hold the signal LOW when AM62x IO buffers are not active.
62_OSPI_4✓A series resistor footprint is recommended on OSPI0_CLK line close to OSD62x-PM device. A 22 Ohm resistor may be necessary to improve signal integrity.
62_OSPI_5✓Per the OSPI protocol, the FLASH device drives DQS while CS is asserted. When CS is not asserted the FLASH device presents HiZ on DQS. When configured to use DQS, the controller uses DQS as a clock, which samples the incoming data into a FIFO. Noise on the DQS when it is HiZ can cause spurious false triggering of the FIFO and filling it with invalid data. There is no way to clear this data except to reset the OSPI module. To avoid this issue, it is recommended to add a pull down on the DQS line.
62_OSPI_6✓It is recommended to add external pullups for CS pin and INT# pin (close to attached device).
62_OSPI_7✓Connecting an OSPI0 interface to multiple memory devices is currently not supported. Connect the OSPI0 interface (processor) to a memory device. In case the OSPI0 is interfaced to multiple memory devices, the interface creates a split data bus which can severely degrade signal integrity at higher speeds. For accessing OSPI memory device at high speeds, a point-to-point connection of the data bus is recommended.
15.

OSD62x-PM Ethernet

Topic NumberOSD62x-PMChecklist Topic
62_ETH_1✓RGMII interfaces of AM62x SOC belong to VDDSHV2 IO domain. It is recommended to connect VDDSHV2 and the IO supply rail of the attached Ethernet PHY device to the same supply source.
62_ETH_2✓MDIO pin must be pulled up.
62_ETH_3✓It is recommended to add series resistors to TX and RX signals near to their origin device to improve signal integrity.
62_ETH_4✓It is recommended to add a pull at the PHY RESET pin opposite to RESET level of the PHY to make sure PHY is held in reset before all power rails are up.
62_ETH_5✓Check PHY datasheet for IO pin strapping needed to configure the PHY in the proper mode based on use case.
62_ETH_6✓Check the IO level of reset source of Ethernet PHY and make sure it is the same as the IO level of the PHY input. If not, a level translator may be needed.
62_ETH_7✓It is possible to generate the clock for Ethernet PHY with AM62x clock outputs. 50MHz clock output for RMII interface can be generated using CLKOUT0 function the EXT_REFCLK1 pin. However, software will need to configure the appropriate PLL, internal multiplexing, and the respective PADCONFIG register before this clock will be sourced from the pin. Most PHYs require a valid clock before reset is released, so you will need design your system to hold the PHY in reset until the clock is valid.

For 25MHz clock output for RGMII, AM62x device will automatically begin sourcing the device reference clock (MCU_OSC0) to the WKUP_CLKOUT0 pin as soon as the device is released from reset (MCU_PORz 0?1).
16.

OSD62x-PM All Interfaces

Topic NumberOSD62x-PMChecklist Topic
62_ALL_1✓All IOs used for a single peripheral interface must belong to the same IOSET. TI’s SYSCONFIG tool provides the IOSET information for each peripheral.


Diagram


You will need to select “Reserve Peripherals” section.
62_ALL_2✓The following signals are recommended as test points:

Power rails: VDD_CORE, VDDA_CORE_CSIRX0, VDDA_CORE_USB, VDD_CANUART, VDDR_CORE, DDR_VPP, VDDA_1P8_CSIRX0, VDDA_1P8_OLDI0, VDDA_1P8_USB, VDDA_PLL[0-2], VDDA_MCU, VDDS_OSC0, VDDA_TEMP, VDDA_3P3_USB, VDDS_DDR, VDDSHV_CANUART, VDDSHV_MCU, VDDSHV[0-6]

Clock and Reset: MCU_RESETSTATz, RESETSTATz and PORz_OUT, EXTINT, MCU_ERRORn, MCU_PORz, MCU_RESETSTATZ, MCU_RESETZ, WKUP_CLKOUT0

IO: PMIC_LPM_EN0, UART0_RXD, UART0_TXD
62_ALL_3✓When a trace is connected to the processor pads and is not actively driven, a parallel pull is recommended. Pull polarity is design use case dependent. During power-up, processor IO buffers are off and the IOs are in a high impedance state, effectively serving as an antenna that picks up noise. Without any termination, the IOs are high impedance. High impedance means, easy for noise to couple energy on the floating signal trace and develop a potential that can exceed the recommended operating conditions, which creates an electrical over-stress (EOS) on the IOs. Electrostatic discharge (ESD) protection circuits inside the processor are designed to protect the device from handling before being installed on a PCB assembly. When adding pull is not feasible, route the traces away from noisy signals.
62_ALL_4✓For all IOs connected to external devices, review BALL RESET STATE and BALL RESET RELEASE STATE in the data sheet to understand how each IO level behaves during and after reset.
62_ALL_5✓Connecting a capacitor load > 22pF at the output is not recommended on GPIOs.
62_ALL_6✓Leave NC and RSVD pins unconnected.
62_ALL_7✓Make sure all interface connectors that connect off board have ESD protection
62_ALL_8✓Never set the Receive buffer (RXACTIVE bit in PADCONF register) on without a valid logic state sourced to the pin that is associated with the respective PADCONFIG register. A floating input can damage the processor or affect reliability.
62_ALL_9✓Valid supply voltage for IO domains must be present before applying inputs to the associated processor IOs or peripherals.
62_ALL_10✓In case the processor and the attached devices or an additional processor are powered by different power sources, signal isolation is recommended because most of the processor IOs are not fail-safe.
62_ALL_11✓OBSCLK0, OBSCLK1, MCU_OBSCLK0 are observation clock outputs for test and debug purposes only. OBSCLK pins can be used to select one of the several different clocks as output.
62_ALL_12✓Should never connect any bidirectional IO directly to the power rail. There is a good chance the device output buffer would be damaged if the pin is connected directly to 3.3V and the output buffer is accidentally driven low.
62_ALL_13✓Check ball reset state and ball reset release state for IOs used to connect to external devices to make sure the reset states don’t affect the connected device. This information is in “Pin Attributes” table of AM625 Datasheet.
62_ALL_14✓The design must make sure the transient overshoot and undershoot on an IO pin does not exceed 0.2*VDD (VDD is the corresponding IO level – 3.3V/1.8V).
62_ALL_15✓The following IO pins are Fail-safe, i.e, they can have voltage applied to them without their IO supply domain (VDDSHV) being powered:

MCU_I2C0_SCL, MCU_I2C0_SDA, WKUP_I2C0_SCL, WKUP_I2C0_SDA,

EXTINTn, VMON_1P8_SOC, VMON_3P3_SOC, VMON_VSYS, and MCU_PORz

The rest of the IOs are not fail safe. They must not see any voltage before the corresponding IO supply domain (VDDSHV) is powered.
62_ALL_16✓ Steady state max voltage for all IO pins except for MCU_I2C0, WKUP_I2C0 and EXTINTn = -0.3 to IO supply (VDDSHV) + 0.3

Steady state max for MCU_I2C0, WKUP_I2C0 and EXTINTn (fail safe IOs) at 1.8V IO level is -0.3 to 1.98, at 3.3V IO level is -0.3 to 3.63V

The voltage specifications for steady state voltage on any IOs must not be violated to prevent damage to the silicon.
62_ALL_17✓RESET signals to various devices on board must match the IO voltage of AM62x pins used to reset them.
17.

Additional Resources

Revision NumberRevision DateChangesAuthor
107/07/2025Initial ReleaseNeeraj Dantu
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