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OSD62x-PM Power Application Note

Published On: December 17, 2025 By: Greg Sheridan

1.

Introduction

This application note provides detailed information on the power design methodology for the OSD62x-PM System-in-Package. It covers power inputs, sequencing, voltage grouping, and low-power design considerations. For a complete implementation example using the OSD62-PM-BRK reference platform, refer to the OSD62x-PM Example Power Design Application Note.

In this application note, we will cover the following topics:

  1. Power overview of the AM62x SoC and OSD62x-PM System in Package
  2. Power design methodology for the OSD62x-PM System in Package
  3. Low power modes

Table of Contents

2.

OSD62x-PM Power Overview

OSD62x-PM integrates the AM62x SoC, DDR4 high-speed memory, and associated passives. The following high-level block diagram shows how the two main internal components are connected.

OSD62x-PM Block Diagram
Figure 1: OSD62x-PM Block Diagram

The OSD62x-PM exposes the power rails of the AM62x SoC and the DDR4 high-speed memory via BGA balls. This allows for a highly customizable power architecture. All processor – DDR connections are made inside the OSD62x-PM System in Package. The two DDR power inputs are the only required external DDR4 connections.

The following table shows the DDR specifications:

Table 2‑1: OSD62x-PM DDR4 Specifications

ParameterValue
Interface width1GBx16
2GBx16
Maximum operating frequency800MHz (1600MTs)
DDR Supply voltage (VDDS_DDR)1.2V nominal
DDR VPP voltage (DDR_VPP)2.5V nominal
2.1.

OSD62x-PM Power Inputs

The following figure shows the power inputs to the OSD62x-PM System in Package.

Figure 2: OSD62x-PM Power Inputs

Most power inputs are required and power various subsystems of the SoC and DDR components.  However, some power inputs are optional if peripherals such as the CSI Camera Interface (CSIRX0) or USB are not used.  As seen in Figure 1, VDDS_DDR of the AM62x and VDD and VDDQ of the DDR4 are connected internally, they form one input power rail for OSD62x-PM.

There are nine (9) IO voltage domain inputs that allow the user to configure the IO voltages of the banks they power (either 1.8V or 3.3V). The associated capacitors (CAP_VDDSx) are integrated within the OSD62x-PM. The USB, and CSIRX0 subsystems have independent power domains to allow for isolation and can be turned off if needed. Additionally, the CANUART subsystem (VDD_CANUART) can be powered independently from all the other power supplies to make use in which only the CANUART domain is operational and the rest of the SoC is turned off.

There are several analog inputs for PLLs that may require external filtering based on use case. Additionally, there are several voltage monitor (VMON) inputs that allow the user to monitor up to three power supplies:  SYS, 3.3V, and 1.8V. Lastly, the VPP power input needs to be supplied by a controllable power supply to meet the sequencing requirements when AM62x OTP programming is in progress.

The following table shows the input specifications of each power rail of OSD62x-PM device.

Table 2‑2: OSD62x-PM Power Rail Specifications

Voltage Rail DescriptionMaximum current rating (mA) Mode Voltage (V)
VDD_CORECore supply 2700 0.85V operation
0.75V operation		 0.75
0.85
VDDA_CORE_CSIRX0CSIRX0 core supply
VDDA_CORE_USBUSB core supply
VDD_CANUARTCANUART core supply 10
VDDR_CORESRAM supply 150 0.85
VDDS_DDRDDR supply 800 1.2
VDDS_OSC0MCU_OSC0 supply 5 1.8
VDDA_MCURCOSC, POR, POK, and MCU PLL analog supply 30
VDDA_PLL0MAIN PLL, DDR PLL, DSS PLL0, and DSS PLL1 analog supply 150
VDDA_PLL1PER0 PLL and PER1 PLL analog supply
VDDA_PLL2ARM0 PLL and SMS PLL analog supply
VDDA_1P8_CSIRX0CSIRX0 1.8 V analog supply
VDDA_1P8_OLDI0OLDI0 1.8 V analog supply
VDDA_1P8_USBUSB0 and USB1 1.8 V analog supply
VDDA_TEMPTEMP analog supply
VPP(1)OTP ROM programming supply 400During OTP programming(2) 1.8
Normal operation 0
VMON_1P8_SOCVoltage monitor input for 1.8V SoC power supply 1.8
VDDA_3P3_USBUSB0 and USB1 3.3 V analog supply 50 3.3
VMON_3P3_SOCVoltage monitor input for 3.3V SoC power supply
VMON_VSYS(3)Voltage monitor input
USB0_VBUS(4)
USB1_VBUS(4)		VBUS input for USB interface
VDDSHV_CANUARTIO supply for CANUART 10 1.8V operation
3.3V operation		 1.8
3.3
VDDSHV_MCUIO supply for MCU 30
VDDSHV0IO supply for IO group 0 150
VDDSHV1IO supply for IO group 1
VDDSHV2IO supply for IO group 2
VDDSHV3IO supply for IO group 3
VDDSHV4IO supply for IO group 4
VDDSHV6IO supply for IO group 6
VDDSHV5IO supply for IO group 530
  1. If there is no hardware support for OTP ROM programming, this signal can be left unconnected.
  2. Make sure the slew rate for this voltage input for OTP ROM programming is < 6E + 4 V/s.
  3. VMON_VSYS pin provides a way to monitor the system power supply. For more information, see Section “System Power Supply Monitor Design Guidelines” in AM62x Datasheet.
  4. An external resistor divider is required to limit the voltage applied to this device pin. For more information, see Section “USB Design Guidelines” in AM62x Datasheet.
2.1.1.

VDD_CORE vs Frequency Requirements

The AM62x SoC does not support Dynamic Voltage Scaling (DVS), so VDD_CORE voltage needs to be chosen corresponding to the operating frequency of the core. The following table shows the VDD_CORE voltage setting and corresponding maximum frequency for the A53 cores:

Table 2‑3: VDD_CORE voltage vs A53 core frequency

Operating Voltage (VDD_CORE)Maximum A53 Frequency
0.85V1.4GHz
0.75V1.2GHz
2.1.2.

Power Rail Grouping

There are several power rails that have the same voltage specification. Some of these power rails can be grouped together to consolidate the power system for lower cost and area. On the other hand, some of the rails can also be dynamically controlled and need to be individually switchable to make use of AM62x low power modes. So, power architecture of the system must be targeted for the specific application requirements. The maximum current for each rail is also listed in the table above. This specification helps with budgeting power rails and matching them with regulators that have output specifications that match the power rail requirements.

2.1.3.

Slew Rate Requirements

In addition to the above specifications, the AM62x SoC has power rail slew rate requirements. All power rails must have a slew rate of < 18mV/us.

2.1.4.

Power Interface IO Pins

The OSD62x-PM has several IO pins whose function is to interface with the power system or control power and reset sequencing for external devices in the rest of the system. The following table provides a description of these pins along with notes on how to use them.

Table 2‑4: OSD62x-PM Power IO Pins

OSD62x-PM/AM62x Signal NameDescriptionUsage
PMIC_LPM_EN0Dual-function PMIC control output, Low Power Mode (active LOW) or PMIC Enable (active HIGH)Can be used to signal low power mode enable to the power system
EXTINTNExternal Interrupt to AM62x SoCCan be used by the power system to signal faults/events to AM62x SoC
MCU_PORZMCU Domain cold resetMain Power on Reset input that must be released after all power rails are stable
MCU_RESETZMCU Domain warm resetCan be used to issue a warm reset to the device MCU domain
PORZ_OUTMain Domain POR status outputCan be used to put other devices in RESET while AM62x is in Power on Reset state
RESETSTATZMain Domain warm reset status outputCan be used to put other devices in RESET while AM62x is in RESET state
MCU_RESETSTATZMCU Domain warm reset status outputCan be used to put other devices in RESET while AM62x MCU domain is in warm RESET state
RESET_REQZMain Domain external warm reset request inputCan be used to request a warm reset of the SoC
MCU_ERRORNError signal output from MCU DomainCan be used to signal an external device that the SoC has encountered an error
2.1.5.

Power Sequencing

Depending on the use case, there are power sequencing requirements for the power inputs. The following figure shows the power up sequencing requirements for the OSD62x-PM.

OSD62x-PM Power Sequencing
Figure 3: OSD62x-PM Power Sequencing

The following table shows the operating voltage for each power input.

Table 2‑5: OSD62x-PM

Operating VoltagePower Input
1.8V onlyVDDA_MCU, VDDS_OSC0, VDDA_PLL0, VDDA_PLL1, VDDA_PLL2, VDDA_1P8_CSIRX0, VDDA_1P8_USB, VDDA_TEMP0, VDDA_TEMP1
1.8V or 3.3VVDDSHV_CANUART, VDDSHV_MCU, VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3
3.3V onlyVDDA_3P3_USB
1.8V & 3.3V(1)VDDSHV4, VDDSHV5, VDDSHV6
  • These rails were designed to support power-up, power-down, or dynamic voltage change without any dependency on other power rails. This capability is required to support UHS-I SD Cards.

 

Important things to note regarding power sequencing for the OSD62x-PM:

  1. The recommendation for the delay between power supply ramp and MCU_PORz release is > 9.5ms
  2. The potential applied to VDDR_CORE must never exceed the potential applied to VDD_CORE +0.18V during power-up or power-down. The sequencing requires VDD_CORE to ramp up before VDDR_CORE and ramp down after VDDR_CORE when VDD_CORE is operating at 0.75V. As noted in the above figure, they can be ramped together when VDD_CORE is set to 0.85V
  3. When VDD_CANUART is connected to an always-on power source, never apply a potential to VDD_CORE which is greater than the potential applied to VDD_CANUART + 0.18V during power-up or power-down. The sequencing requires VDD_CANUART to ramp up before VDD_CORE and ramp down after VDD_CORE. As noted in the above figure, they can be ramped together when Partial IO mode is not used.
  4. TI recommends limiting the maximum slew rate of supplies to be less than 18 mV/µs.
2.1.6.

Partial IO Power Mode

The only power mode that requires a change in the power sequence is the partial IO power mode. In this mode, VDD_CANUART and VDDSHV_CANUART are supplied with an independent power supply. These power rails need to follow the power up sequencing described above but can remain powered ON when all other rails are turned OFF.

2.1.7.

Power Down Sequencing

The following figure shows the requirements for the power-down sequence.

Important things to note regarding power-down sequence of OSD62x-PM:

  1. VDD_CANUART and VDDSHV_CANUART can stay ON after the rest of the power rails turn OFF.
  2. VDDR_CORE needs to turn OFF either before VDD_CORE or along with VDD_CORE.
  3. VDD_CORE needs to turn OFF either before VDD_CANUART or along with VDD_CANUART
Figure 4: OSD62x-PM Power Down Sequencing
2.1.8.

Unused Subsystems

Based on application requirements, some subsystems on AM62x SoC can be turned OFF to save power. See the following table for details on which subsystem can be turned OFF by connecting the corresponding power rails to GND.

Table 2‑6:Recommendations for Unused Power Rails

SubsystemPower rails that can be connected to GND if unused
USB0 and USB1VDDA_CORE_USB, VDDA_1P8_USB, VDDA_3P3_USB
CSIRX0 (If boundary scan is not used)VDDA_CORE_CSIRX0, VDDA_1P8_CSIRX0
2.1.9.

Using VPP Input to Program OTP Registers

AM62x SoC contains One-Time Programmable (OTP) registers that can be programmed with information such as security keys. The power supply that provides power to the VPP power input must be controllable by the processor in order to meet the timing and sequencing requirements.  The following steps are required from a power sequencing perspective to program the registers and are handled by the software provided by TI:

  1. Power on the board per the power-up sequencing. No voltage should be applied on the VPP terminal during power up and normal operation.
  2. Load the OTP write software required to program the registers.
  3. Apply the voltage on the VPP terminal according to the specification in Table 2‑2.
  4. Run the software that programs the OTP registers.
  5. After validating the content of the OTP registers, remove the voltage from the VPP terminal.
3.

Power Design for OSD62x-PM

There are two main ways to design a power system for the OSD62x-PM:

   1. Using a Power Management IC (PMIC).
  2. Using Discrete Regulators.

Along with guidelines from TI, Octavo Systems provides the following guidelines when selecting discrete regulators for theOSD62x-PM SiP:

    1. Power supplies must be configured to the required voltage level of the SiP and must always operate in the Recommended Operating Conditions of the OSD62x-PM SiP   power input.

   2. Power supplies must follow the power-up and power-down sequencing according to the specifications in Section.

   3. Power supplies must meet the slew rate requirements outlined in Section 2.1.3.

   4. All power rails must be fully powered up before MCU_PORz reset is released.

   5. There must not be any residual voltage (<0.3V) on any power rails before the power supplies are turned ON.

   6. MCU_PORz release must be glitch free.

   7. Power rails can be grouped based on the operating voltage and power sequencing requirements.

   8. Voltage monitor inputs must be connected as specified in Section 2.1.

  9. Configure power sequencing/grouping based on whether Partial IO low power mode is used.

  10. Power supplies must be able to support the current requirements of the power rail / group of power rails they are powering.

  11. Some power supplies, for example a supply powering a UHS-1 SD card interface, must be able to switch between 3.3V and 1.8V and must be IO controlled.

  12. The supply powering the VPP voltage input must have controllable voltage output.

3.1.

Discrete Power System

TI provides a reference discrete power solution for the AM62x SoC that can also be used for the OSD62x-PM device. The application note describing the solution is located here: https://www.ti.com/lit/an/sluaak2/sluaak2.pdf. This solution may need to be modified based on the user application requirements. For example, VDDSHV_CANUART and VDD_CANUART may need an extra always-ON regulator to support Partial IO power mode. Additionally, current requirements in specific applications may differ based on the power rail grouping. Sequencing of the power rails can be achieved using the PGOOD outputs of regulators, gating logic, RC delay circuits, and SoC IO.

For reference, the block diagram describing this solution is provided below:

Example Discrete Power Solution for OSD62x-PM
Figure 5: Example Discrete Power Solution for OSD62x-PM

A reference design based on discrete power system for AM62x SoC is located here: https://www.ti.com/tool/SK-AM62#design-files. The reference design uses DDR4 memory making the power system compatible with OSD62x-PM based on design requirements.

3.2.

TI PMIC Based Power System

TI provides the TPS65219 Power Management IC (PMIC) that is a perfect companion for the AM62x SoC and the OSD62x-PM SiP. The TPS65219 PMIC integrates three (3) DC-DC Buck convertors and four (4) LDO regulators and can be used to generate all the voltages needed to power the OSD62x-PM according to specifications. The following table provides an overview of the outputs along with their capabilities:

TSPS65219 OutputInput Voltage RangeOutput Voltage RangeCurrent Capability
BUCK12.5 V – 5.5 V0.6V – 3.4V3.5A
BUCK22A
BUCK32A
LDO11.5V – 5.5V (LDO/Load switch)
1.5V – 3.3V (Bypass)		0.6V – 3.4V (LDO)
1.5V – 3.4V (Bypass)
400mA
LDO2400mA
LDO32.2V – 5.5V1.2V – 3.3V300mA
LDO4300mA
3.2.1.

TPS65219 Features

The following features of TPS65219 make it a good target to power the OSD62x-PM device:

  1. Wide input voltage range
  2. Buck regulators to target high current power rails targeting high efficiency
  3. LDOs to target analog and other noise susceptible power rails
  4. I2C interface for communication and configuration during run time
  5. General Purpose Output pins to control and coordinate sequencing with other regulators in the power system
  6. Standby and mode control pins for low power modes and power saving operations
  7. Configurable power button input and reset input for control
  8. Interrupt output to signal power related faults to the AM62x SoC and reset output pin to bring the AM62x SoC out of reset after power sequencing
  9. Configurable power sequencing that satisfies the OSD62x-PM power-up and power-down sequencing requirements
  10. Input voltage monitoring with under-voltage and over-voltage fault detection and response
  11. Output regulator voltage fault detection:
    • Under-voltage detection and response
    • Over-current detection and response
    • Short to ground detection and response
    • Residual voltage detection and response
  12. Dynamic voltage switching support for 1 LDO to support UHS-1 SD cards
  13. Thermal warning and shutdown
  14. Active discharge of output power rails
3.2.2.

TPS65219 Operating States

TPS65219 has four (4) operating states:

  1. OFF state: All logic is OFF. PMIC enters INITIALIZE state when it detects VSYS > SYS_POR threshold
  2. INITIALIZE state: PMIC reads the internal EEPROM memory and loads the registers to their default values. The power-up sequence can only execute after the EEPROM-load and if all rails are discharged below VBUCKx_SCG_TH/VLDOx_SCG_TH = 300mV. The PMIC needs the EN/PB/VSENSE input to go from this state to ACTIVE state unless the FSD (First Supply Detection) feature is enabled.
  3. ACTIVE state: All enabled buck converters and LDOs are operational and can be controlled through the I2C interface. If a shut-down-fault (SD_Fault) occurs while in the ACTIVE state, the TPS65219 sequences down the active outputs and transition to the INITIALIZE state. The device does transition to ACTIVE state without a new Push-button-ON_Request.
  4. STBY state: Low power mode with pre-configured set of power rails ON required for SoC in this state. Can be entered by using I2C command or usage of STBY pin.

Here is the State Diagram from TPS65219 datasheet for reference:

Figure 6: TPS65219 State Diagram
4.

Low Power Modes

The following are the low power modes the OSD62x-PM supports:

  1. Partial IO
  2. Deep Sleep
  3. MCU only
  4. Standby
4.1.

Partial IO Mode

The entire SoC and DDR is OFF except I/O pins in CANUART I/O Bank.  This allows wakeup capability from CANUART I/O pins. To support this mode, VDDSHV_CANUART and VDD_CANUART must be powered separately from an always ON regulator. This is the only mode that requires explicit hardware design to support it. The system loses nearly all of its current state as DDR is OFF. Partial I/O is comparable with a Linux “poweroff” state.

4.2.

Deep Sleep Mode

In this mode, power supplies stay ON, but all on-chip power domains are shut OFF except for the always on domains. The DDR is put in self-refresh mode. This is the lowest power mode that allows for fast wake-up. The peripheral and MPU context must be saved in the DDR before entering this mode. When a wake-up event is detected, the boot ROM checks whether the device is waking from this mode and initiates a DDR resume process.

4.3.

MCU-Only Mode

In this mode, the state of the SoC is the same as deep sleep except the MCU domain is ON. The DDR is put in self-refresh mode, but the MCU domain can run applications and use MCU domain peripherals. In addition to the wake-up sources for deep sleep mode, the MCU can generate a wake-up condition to the SoC to exit out of this mode.

4.4.

Standby Mode

In this mode, all modules are clock gated except for the GPIO.  The DDR is put in self-refresh mode. All power domains are powered ON, but the PLLs may be put in bypass mode. GPIOs can be used to generate an interrupt to the device manager to wake up from this low power mode. If any other peripheral needs to wake up the device from this power mode, the PLL to the peripheral must be kept ON and it must be configured to generate an interrupt to the device manager core.

4.5.

Wake-up Sources

The following table shows the valid wake-up sources for each low power mode of the OSD62x-PM:

Table 4‑1: AM62x SoC Wake-up Sources

Wake-up SourceDeep SleepMCU-onlyPartial IO
Real-Time Clock (RTC)YesYesNo
MCU (WKUP) GPIOYesYesNo
Main I/O Daisy Chain (Main GPIO and Main UART)YesYesNo
USB WakeupYesYesNo
WKUP UARTYesYesNo
MCU IPC (for MCU Only mode)NoYesNo
CAN UART I/O Daisy ChainYesYesYes
4.6.

Dynamic Frequency Switching

In addition to the low power modes, the CPU frequency can be used to fine tune power consumption based on the use case. This is done by defining operating performance points (OPPs) at different frequencies for the A53 cores. The table below shows the list of possible CPU frequencies while in the active state.  Since, the AM62x SoC does not support dynamic voltage scaling, 1400 MHz can only be achieved by having the device boot with a core voltage of 0.85V.

Table 4‑2: AM62x SoC Frequency Scaling

VDD_CORE Voltage (V)A53 Core Frequency (MHz)
0.75 or 0.85200
400
600
800
1000
1250
0.85 only1400
5.

Additional Resources

  • AM62x Maximum Power Ratings

https://www.ti.com/lit/an/sprada6/sprada6.pdf

  • TI System Control Interface overview

https://software-dl.ti.com/tisci/esd/latest/1_intro/TISCI.html

  • AM62x Boot flow

https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/latest/exports/docs/linux/Foundational_Components/U-Boot/UG-General-Info.html#boot-flow

  • Power supply design guide

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1337814/faq-am625-am623-am620-q1-am62l-am62ax-am62d-q1-am62px-am64x-am243x-design-recommendations-commonly-observed-errors-during-custom-board-hardware-design-soc-peripherals-and-ios-connection-when-not-used

  • Discrete Power System design for OSD62x-PM

https://www.ti.com/lit/an/sluaak2/sluaak2.pdf

  • PMIC based power system design for OSD62x-PM

https://www.ti.com/lit/an/slvafd0b/slvafd0b.pdf

  • AM625 Datasheet

https://www.ti.com/lit/pdf/SPRSP58

  • Hardware Design Considerations for Custom Board using AM625

https://www.ti.com/lit/pdf/SPRAD05

  • Sitara Processors Power Distribution Networks

https://www.ti.com/lit/pdf/SPRAC76

  • AM62x Power Estimation Tool User guide

https://www.ti.com/lit/pdf/SPRAD31

  • AM625 Schematic Design Guidelines and Review Checklist

https://www.ti.com/lit/pdf/SPRAD21

6.

Revision History

Revision NumberRevision DateChangesAuthor
16/25/2025Initial ReleaseNeeraj Dantu
Erik Welsh
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