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Published On: October 31, 2025 By: Neeraj Dantu
The OSD62x-PM System in Package (SiP) was designed to minimize the number of Printed Circuit Board (PCB) layers and eliminate design complexity of high speed DDR4 memory in AM62x SoC based designs. By moving the most error-prone portion of the design, the high-speed memory layout, inside the package, the SiP lets your PCB focus on power integrity, signal escape, and robust high-speed I/O.
While the SiP removes major risk in your AM62x based designs, the following aspects of a custom design need special attention to make sure an optimal design is achieved:
In this application note, the following topics are covered:
Other application notes that should be helpful in conjunction with this one:
The Ball Map shown in Figure 1 provides a visual representation of the arrangement of the pins (Top View) of the OSD62x-PM. This can help with the placement and orientation of the OSD62x-PM in a design.
Important OSD62x-PM footprint parameters are shown in Figure 2 (Top View) and listed in Table 2‑1.
| Parameter | Value |
|---|---|
| Package Dimensions | 9mm x 14mm x 1.3mm |
| Number of BGA balls | 500 |
| Ball Grid Layout | 18 rows x 28 columns |
| Ball Pitch | 0.5mm (19.685mils) |
| Ball Diameter | 0.25mm (9.84252mils) |
| Landing Pad Size | 0.2mm (7.87402mils) |
For more information on the footprint configuration, please see the Mechanical Dimensions section of the OSD62x-PM datasheet.
To find more information about IPC-7351A specifications, refer BGA Ball Pad Size section of BGA PCB Design document from Texas Instruments (TI). Below is a picture of the table in the IPC-7351A specification that describes landing pad size based on BGA ball diameter:
The simplification of design that the OSD62x-PM provides changes how you should think about the signal and power fan-out: you can spend stack-up and via budget on clean power/ground escapes, low-inductance returns, and high-speed I/O quality instead of using layers on high-speed DDR memory. This section will provide information on the optimum size of traces and vias and gives you practical patterns to escape the BGA cleanly.
The number of traces that can pass between any two pads of a BGA footprint depends on the trace width and trace spacing. Trace width is the actual width of the trace. Trace spacing is the distance between the edges of any two adjacent traces or a trace and a pad. Trace width and trace spacing are shown pictorially in Figure 4.
In this document, a “x/y trace” indicates a PCB that uses design rules with trace width of x mils and trace spacing of y mils. For example, a 5/6 trace indicates a PCB with trace width of 5mils and trace spacing of 6mils.
The number of traces that can be routed between any two adjacent pads of the BGA can be calculated using the formula (assumes all the traces are equal width):
where,
tn = number of traces
tw = trace width
ts = trace spacing
BP = BGA pitch
BD = BGA ball diameter
For example, calculating the number of 3/3 traces that can be routed between adjacent pads of the OSD62x BGA: tw = 3mils, ts = 3mils, BP = 19.685mil (0.5mm) and BD = 7.87402mil (0.20mm)
Using all this in the above equation:
This result indicates that one (1) full 3/3 trace can be routed between adjacent balls of the OSD62x-PM BGA. The number of traces can be calculated for other routing rules.
The following table shows possible configurations for minimum trace width and spacing corresponding to the landing pad diameter used for the footprint.
| Footprint Landing Pad Size | Minimum Trace Width/Trace Spacing for OSD62x-PM |
|---|---|
| 0.2mm (nominal) | 3.5mil (0.0889 mm) |
| 0.17mm (minimum) | 4mil (0.1016 mm) |
The following figure shows an example escape the BGA for the OSD62x-PM in the OSD62-PM-BRK layout using a 3/3 trace width/trace spacing.
There are two important parameters for vias: drill diameter and annular ring thickness. Drill diameter is the diameter of the drilled hole in the PCB. The annular ring thickness is the thickness of the pad that surrounds the drilled hole. These dimensions are shown in the following figure:
To determine the diameter of the finished via, use the following formula:
Finished via diameter = Drill diameter + 2 x (Annular ring thickness)
Via spacing is the distance between the edges of any two adjacent vias as shown in the below figure. When placing vias, make sure the spacing between the vias matches the trace spacing design rules that were chosen.
In this document, a “x/y via” indicates a via with drill diameter of x mils and finished via diameter of y mils. For example, a 12/24 via indicates a via with drill diameter of 12mils and finished via diameter of 24mils (i.e. an annular ring of 6mils).
In general, there are 3 possible configurations for vias within a BGA array:
These variations in layout are shown in the following figure:
However, given the 0.5mm pitch, we recommend only using configuration 1 due to the drill and via sizes required.
The following table shows the maximum via size (Drill diameter + 2 x (Annular ring thickness)) that can be achieved for 1 via configuration shown in Figure 8.
| Trace Width/Trace Spacing Rule (mil/mil) | Maximum Via Size (mil) = Drill diameter + 2x (Annular ring thickness)* |
|---|---|
| 3/3 (0.0762 mm / 0.0762 mm) | 13.96 (0.3547 mm) |
| 3.5/3.5 (0.0889 mm / 0.0889 mm) | 12.96 (0.3293 mm) |
| 4/4 (0.1016 mm / 0.1016 mm) | 11.96 (0.3039 mm) |
* These calculations assume a nominal landing pad size of 0.2mm
Please note that these via sizes only account for top size structures and to not necessarily allow for bottom side routing between vias. Please see the next section for limitations on vias if bottom side routing is required.
The OSD62x-PM was designed so that the third and fourth rows/columns need vias to be routed on a different layer than the first and second rows/columns. In a 4-layer PCB design this would typically be done on the bottom layer. In this case, if all traces of the package are being escaped, there is a need to route the trace of the signal from the fourth row between 2 vias used to escape the third row. This is shown below in Figure 9.
The following table shows the maximum via size (Drill diameter + 2x (Annular ring thickness)) that can be achieved for the via configuration shown in Figure 9.
| Trace Width/Trace Spacing Rule (mil/mil) | Maximum Via Size (mil) = Drill diameter + 2 x (Annular ring thickness)* |
|---|---|
| 3/3 (0.0762 mm / 0.0762 mm) | 10.68 (0.2714 mm) |
| 3.5/3.5 (0.0889 mm / 0.0889 mm) | 9.18 (0.2333 mm) |
| 4/4 (0.1016 mm / 0.1016 mm) | 7.68 (0.1952 mm) |
* These calculations assume a nominal landing pad size of 0.2mm
In general for 1oz copper PCB designs, we recommend using a 0.2mm nominal landing pad size, 10 mil (0.254mm) finished via size, and 3.2/3.2 mil (0.8128 mm) trace / space to escape the BGA array. However, the final determination of trace width, trace spacing, via drill and annular ring size should be made in conjunction with the chosen manufacturer according to their specifications.
This section will focus on the strategies to optimize PCB area and reduce layer count when laying out the OSD62x-PM. As a practical example, OSD62-PM-BRK board is used to showcase these strategies. The guidelines in the section are general recommendations and do not account for the specific needs of all designs. Depending on the manufacturer’s PCBA capabilities and the specific mechanical, thermal, and electrical needs of the design, these strategies may need to be customized.
The following table shows the relevant design rule specifications for OSD62-PM-BRK:
| Parameter | Value |
|---|---|
| Layer Count | 4 |
| Component population | 1 sided(1) |
| Material | FR4-TG175 |
| Copper Weight | 1oz |
| Board Thickness | 1.6mm |
| Trace Width | 3mil (0.0762 mm) |
| Trace Spacing | 3mil (0.0762 mm) |
| Drill Size | 4mil (0.1016 mm)(2) |
| Annular Ring | 3mil (0.0762 mm)(2) |
(1)The OSD62-PM-BRK does not have any bottom side passives
(2)Total via size is 10 mil (0.254mm). Other manufacturers may have different Drill Size/Annular Ring tradeoffs (e.g. 6mil (0.1524mm) Drill Size and 2mil (0.0508 mm) Annular Ring)
The following figure shows the stack-up of OSD62-PM-BRK (Standard 1.6mm thickness; 1oz copper):
The following image shows the fanout of the OSD62x-PM on the OSD62-PM-BRK on layers 1 (top) and 4 (bottom). This fanout allows for escape of 4 outer rows of the BGA package with 3/3 trace/space routing on 2 layers. This is a comprehensive fanout for the OSD62x-PM because all IO of AM62x SoC are routed out of the package.
Figure 12 shows fanout of IO in top and bottom layers at a corner of OSD62x-PM detailing the 4 outer row escape under OSD62x-PM BGA. The outer 2 rows are routed through the top layer and the bottom layer is used for the inner 2 rows as shown below.
The following figure shows the power input rails of OSD62x-PM on the footprint:
It is important for all power inputs to satisfy the current, voltage, and noise specifications of the OSD62x-PM. For more information on the power inputs and their specifications, please refer to OSD62x-PM Power Application Note.
As shown in Figure 13, thicker traces (6mil in OSD62-PM-BRK) and vias are used to escape these power inputs to layers 3 and 4. Many of these inputs can be powered with the same power rail based on the design requirements. The Power Application Note linked above outlines the requirements and power rail consolidation available based on the requirements.
The following figure shows the power layer routing of OSD62x-PM under the BGA. The 3.3V rail that powers all the IO domains is used as the reference plane on layer 3 (Please note that VDDSHV5, i.e. the IO voltage domain for MMC1, is routed separately due to the ability of the SD card interface and the PMIC to support voltage switching). The plane allows for multiple routes to power all the input rails of OSD62x-PM set to 3.3V. Other rail traces including VDD_CORE and VDDS_DDR are routed through the bottom left corner of the device. Please review your current requirements for each rail to understand the trace width needed for each rail. It is important to make sure that there are no bottlenecks on any power input rails that can lead to in-rush or brownout issues.
Additional routing can be done on layer 4 (bottom) for better connectivity of the power rails:
The ground connections to the OSD62x-PM serve three functions:
OSD62x-PM device has approximately 100 GND pins that can help with the above functions. We recommend the following strategies to help achieve these functions:
The following figure shows the GND plane on layer 2 under OSD62x-PM device:
The OSD62x-PM was designed to have one via per ground pin and still be able to achieve complete fanout and power routing in four layers. Additional vias are recommended when the signal and power routing on layers 3 and 4 allow. Additionally, layer 4 is flooded with GND to provide additional thermal relief for the design as shown below:
There are several high-speed interfaces on OSD62x-PM that require specialized routing to preserve signal integrity and reduce EMI emissions. The following documents provide more information about the requirements for these interfaces:
Please refer to the above documents for additional specifications you need to follow for high-speed interfaces of OSD62x-PM.
No capacitors are required under the OSD62x-PM device, making it possible to achieve a single sided PCB design. However, capacitor requirements for the input power rails are listed in OSD62x-PM Datasheet. These capacitors should be placed as close to OSD62x-PM device as possible, but are not required to be underneath the device.
OSD62x-PM has one required 25MHz clock input. A crystal or an oscillator can be used to generate this clock. An optional clock input of 32KHz is also present and can be used based on design requirements. Both clock sources must be placed as close to OSD62x-PM as possible with minimal trace lengths for the clock signals.
As described in the Power Application Note, there are multiple ways to power the OSD62x-PM device based on design requirements. An example is shown on the OSD62-PM-BRK with TI’s TPS6721903 PMIC. The design files for OSD62-PM-BRK are available as reference or modification here.
| Revision Number | Revision Date | Changes | Author |
|---|---|---|---|
| Revision Number | 10/03/2025 | Initial Release | Neeraj Dantu, Erik Welsh |
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There has been multiple revisions to the OSDZU3-REF and some of the documentation is for specific revisions.
The revision of your OSDZU3-REF is printed under the fan next to the Octavo Systems logo. See the image below.
If there are multiple versions of a document make sure you select the one that matches your revision.
