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Published: December 12, 2025 By: Greg Sheridan
This application note gives an overview of the boot chain for the AM62x SoC inside the OSD62x-PM. It is useful information to have when debugging custom boards.
This section provides information on the boot chain of the AM62x SoC integrated into the OSD62x-PM. The boot procedure for the AM62x SoC involves multiple stages and various CPU cores. The following table describes the part each CPU plays in the boot process:
| M4 (Security Management Subsystem) | R5 (Device Manager) | A53 |
|---|---|---|
| Executes secure ROM | Executes public boot ROM | Boots High Level OS |
| Authenticates boot chain (secure boot) | Loads SPL (Secondary Program Loader) to initialize the SoC and the DDR interface | Runs Applications |
| Runs System Firmware (TIFS) provides secure services | Runs Device Management Firmware and services resource and power management requests | |
| Forwards requests and responses between Device manager and other cores | Forwards requests and responses between non-secure cores and Security Management Subsystem for resource management | |
| Manages firewall for resources requested by secure and non-secure cores |
The following figure shows the boot process of the AM62x SoC:
Here is an overview of the steps involved in the AM62x SoC initialization:
1. System power enables the PMIC / discrete power system.
2. The PMIC / power system raises the power rails according to the power sequence and releases MCU_PORz (i.e. pulls signal high).
3. Boot mode pins are latched upon MCU_PORz release.
4. The Security Management Subsystem (SMS) M4 boots the Secure ROM.
6. The Secure ROM enables the R5 (Device Manager) to boot the Public ROM.
7. The Public ROM loads the R5 SPL (Secondary Program Loader – part of tiboot3.bin) and authenticates it with the SMS.
8. Upon Authentication, the Public ROM passes control to the R5 SPL.
9. The R5 SPL initializes TIFS (TI Foundational Security) Services on SMS.
10. The R5 SPL initializes the DDR and other AM62x SoC peripherals.
11. The R5 SPL loads the ATF (Arm Trusted Firmware) + OPTEE (Open Portable Trusted Execution Environment) and the SPL for the A53 cores and works with SMS to release A53 cores out of Reset.
12. The R5 SPL loads and starts the Device Manager Firmware and jumps to it to provide resource management and power management services as part of the SCI (System Control Interface).
13. The A53 cores boot ATF + OPTEE which starts execution of the SPL
14. The A53 cores SPL loads and starts execution of U-Boot.
15. The A53 cores U-boot loads and starts Linux Kernel.
The above components use UART ports to send boot logs / debug traces corresponding to the firmware they execute. The following table provides specific UART interfaces used:
| Firmware | Logging interface |
|---|---|
| Main console log output (bootloaders, Linux Kernel) | MAIN_UART0 |
| TIFS | MAIN_UART1 |
| Device Manager Firmware | WKUP_UART0 |
To debug errors during booting, the above interfaces can be used to get feedback from the firmware involved.
| Revision Number | Revision Date | Changes | Author |
|---|---|---|---|
| 1 | 6/25/2025 | Initial Release | Neeraj Dantu Erik Welsh |
There has been multiple revisions to the OSDZU3-REF and some of the documentation is for specific revisions.
The revision of your OSDZU3-REF is printed under the fan next to the Octavo Systems logo. See the image below.
If there are multiple versions of a document make sure you select the one that matches your revision.
