# Category: System-In-Package

## Why System in Package Technology Must Replace System on a Chip Technology

System on a chip (SoC) technology has got us a long way, allowing for entire electronic systems to be integrated into a single microchip, and SoC technology has long been the driving force behind smaller and smaller electronic systems with higher and higher levels of performance. Like all great technologies, though, SoC technology must eventually give way to something even more innovative and effective. In an article published by Stephan Ohr on EE Times, Ohr discusses how the increasing costs of transistor scaling has made SoC technology less viable and has created a demand for a specialized design process, and we at Octavo Systems completely agree with that assessment. With current manufacturing trends demanding an efficient process to manufacture an entire electronic system at one time and at increasingly smaller sizes, SoC technology is no longer an optimal solution. Fortunately, we have  a replacement–System in Package (SiP) technology.

### What is System in Package Technology?

System in Package (SiP) technology is simply combining a number of integrated circuits together in one highly compact module (package) and that function as one unit. In SiP, integrated circuits are attached to a substrate then electrically connected via fine wires within the package. Rather than focusing on how many transistors we can fit onto one piece of silicon, SiP technology aims to develop new and innovative ways to integrate system components into a single package. This is especially valuable in space-constrained designs, and SiP technology has paved the way for smaller and smaller electronic devices by decreasing the complexity of circuit boards and eliminating the need to add a large number of external components in order to make the device function. In this way, SiP technology has been the driving force behind miniaturizing devices that once would have been too complex for SoC methodology to make work.

### Why SiP is Replacing SoC

System in Package (SiP) technology was born out of the overwhelming success of Moore’s Law. Moore’s Law has allowed for the production of semiconductors that are less expensive, dissipate less power, and have higher performance. What it has also done, however, is make it so there is no longer one semiconductor manufacturing process that works for all of the components which

make up a system. For SoC to work at a system level, one or more necessary components will need to be severely compromised. As more devices begin to rely on integrating components into a single system, SoC is losing its viability as a cost efficient, functional option for system integration. SiP, however, opens the door for the design of a near limitless variety of complex systems. While SiP is already a popular methodology in a variety of industries, our goal at Octavo Systems is to promote SiP as the go-to technology for all facets of electronic design.

### Opportunities SiP Provides

One of the biggest opportunities SiP provides is for the production of specialized sensors that will be affordable enough to have potential on the market. One example of such sensors would be smart sensors placed inside of cups at coffee shops. Many coffee shops already provide free internet, encouraging visitors to linger and hopefully order more coffee. However, for a customer to order more coffee they must get up from their seat, leaving their computer behind and risking losing their seat to go stand in line. In this way, ordering more coffee becomes inconvenient for the customers and hurts the coffee shop’s chances of making a sale.

With a smart cup, however, sensors could be integrated into the cup, alerting the barista when the coffee in the cup is almost gone or has grown cold so they can come by with a fresh cup of coffee. The cup then becomes a sort of an “infinity cup” that is continually replenished, and the customer’s credit card charged, without the customer ever having to leave their seat. If the  cup is sold to the customer as a personal cup, the barista could be alerted as soon as the customer walks through the door with the cup and could begin making the customer’s order. Alternatively, the customer could choose to have a menu of drinks for the day, in which case the barista would wait for the customer to place their order as normal.

As the Internet of Things becomes increasingly more of a reality rather than just a concept, the need for a multitude of affordable, highly functional sensors grows more apparent. The SiP methodologies we are pushing for at Octavo Systems help make those sensors possible.

Another great example of the innovations SiP provides can be found in imaging systems. SiP technology allows for devices as complex as a high-resolution camera to be produced at incredibly small sizes. Several years ago I was involved with a medical research team at USC as they were creating artificial vision. The aspect of their research that encouraged me was their designing a camera that could be surgically implanted into the eye of the patient, and the end goal of the project was to produce a camera the size of a grain of rice. Before SiP technology, a camera of this size would not have been possible. However, using the advantages of a SiP solution, the team at USC was able to conceive a viable design that could provide artificial sight to a blind patient.

These two examples are just a small sample of the opportunities involved with embracing SiP technology. We at Octavo Systems believe that SiP technology is soon to become the new poster-child for technological innovation, paving the way for an unimaginable number of new and innovative designs.

## System-In-Package: The Next Step of Integration

Our CTO, Gene Frantz, published an article on Embedded Computing last week titled System-In-Package: The Next Step of Integration. In his article, he poses an interesting question: How do small, innovative companies work with larger semiconductor manufacturers to further integrate their designs?  He outlined four questions that need to be answered “YES” before a large S/C manufacturer will agree to work with any company for a custom integration.

What happens, however, if you can’t answer “YES” to all of them? Are you out of luck?  Is there no path to further integration?  Not quite.  Gene points out that there just might be a way forward with the advances made by Octavo.

I want to take a minute to dive a little deeper into this statement.  Why do we think we can offer an alternative path of integration for innovative organizations?  The answer is simple. There are three key factors that enable us to provide these solutions:

1. Our Culture. Our company was founded by a group of people who’ve spent large chunks of their careers trying to promote innovation within the corporate structure of a large S/C company.  We understand that innovation begins small, and we believe in enabling smaller companies to pursue innovation.
2. Our “Aha!” Moment. Our biggest “aha” moment came when we realized that the ultimate integration takes place as a system level integration of all the transistor types, each on its own die. The obvious solution was to use System in Package (SiP) technology to integrate it all together. We can take the best process for each part of your system and integrate them into a standard IC package, giving you the integration you need.
3. Our Approach. We believe that there are ways to make the high volume S/C manufacturing process work for lower volume opportunities. This means that we can quickly and affordably produce SiPs for you.

In a nutshell, if you have an electronic design and are looking for an integration path, you have two options.  You can go to a large S/C manufacturer to see if you’ll pass their four tests, or you can contact us and see what we can do for you.

## The OSD3358 – A New Era of Integration

Today is a very exciting day at Octavo Systems. We’re officially launching our first product, the OSD3358-512M.  The OSD3358 is a System-In-Package (SiP) device that integrates the Texas Instruments (TI) Sitara™ AM3358 Arm® Cortex®-A8 processor, the TI TPS65217C PMIC, the TI TL5209 LDO, a 512MB DDR3, and over 140 Passives into a single easy to use BGA package. The OSD3358 gives designers of all levels access to unprecedented integration and to ease of use.

The OSD3358 aims to make designing custom systems around the BeagleBone® Black as easy as possible.  Take a look at our Single Board Computer Reference Design.  Integrating the DDR3 and the Power Managements systems into the OSD3358 removes the need for designers to spend time on the DDR to Processor interface or power sequencing, allowing them to focus on their proprietary value add. At the same time, the single package simplifies the supply chain and facilitates lower cost manufacturing.  Check out the product page for all the details.

The OSD3358 isn’t just for BeagleBone® Black users either.  It has the flexibility to greatly simplify any design based on TI’s Sitara™ processors.  So, along with the OSD3358, we also launched, in partnership with GHI Electronics, a set of development boards and kits to allow you to design your own product around the OSD3358 without starting with a BeagleBone®.

What makes today truly special is that we have given substance to our vision.  Historically, SiPs have been available only to the largest and most specialized customers. Today we change that.  Our innovations in design and manufacturing have allowed us to bring SiP-based products to the mass market.  This is the culmination of many efforts. Our Octavo team spent many long nights and weekends to make this day a reality.  I am proud of the entire team and am honored to work with such outstanding individuals.

While we are excited about what we have achieved with Product #1, we are even more enthused about where we’re going.  The OSD3358 is just the beginning.  Over the next few months we will be working to widen the OSD335x family, offering options to fit almost any system built around the AM335x processor.

Beyond that, our goal is to change the way intelligent systems are designed and manufactured.  We will continue our quest to introduce products that make it easier for innovators to innovate.  We will integrate more functions to provide more solutions for a wider variety of subsystems.  We’d love to hear your feedback on what you’d like to see next or what we can do to improve our current product.  Please don’t hesitate to let us know what you think here.

## Octavo Systems Releases the OSD3358 System-In-Package Device

Octavo Systems Helps Bridge the Prototype-to-Production Gap

Austin, Texas (May 9, 2016) – Octavo Systems LLC (Octavo) today launched a new platform that makes it easier than ever for designers to quickly create production-ready systems based on the Texas Instruments (TI) Sitara™ AM335x processor with an ARM® Cortex®-A8 core. The OSD3358, the first in a family of System-In-Package (SiP) devices, is geared to help developers who are using the BeagleBon®e Black single board computing (SBC) platform move from prototype to production effortlessly.

“With the wide availability and strong community around single board computing platforms like the BeagleBone® Black, it is easier than ever for designers to quickly prototype and prove out a design,” said Octavo President Bill Heye. “However, moving past the prototype stage into a production ready product remains very difficult for a large number of people and organizations.”

“After a proof of concept is done on an SBC, an application-specific mainboard will need to be designed, requiring a large number of specialized skills that can be hard to come by,” explained Gene Frantz, Octavo’s CTO. “Our System-In-Package devices reduce this requirement by abstracting some of the most tedious and complex tasks, allowing designers to focus on their end product.”

The OSD3358 is built to make the design of an application-specific mainboard around the Sitara™ AM3358 processor as easy as possible. It integrates the core of the BeagleBone® Black, the AM3358 processor running up to 1GHz, the TPS65217C power management IC (PMIC), the TL5209 low-dropout (LDO) regulator, 512MB of DDR3 memory, and over 140 passive components, into a single BGA package. Through this integration, the OSD3358 removes the complexities of power sequencing and DDR to processor interfacing that are typical in the design process.

The OSD3358 has the smallest footprint of any similar AM3358 processor implementation. It simplifies the sourcing of components and supply chain management by replacing over 144 components with just one. The OSD3358 also utilizes a wide pitch BGA of 1.27mm allowing cost effective manufacturing processes to be used. “These added benefits make the OSD3358 an attractive solution not just for new designs, but also as a way to simplify or cost down an existing design,” added Heye.

“We are very excited that Octavo will be using the scalable Sitara™ AM335x processor as the base of the OSD335x family, giving designers both great performance and simple development,” said Adrian Valenzuela, Marketing Manager, Catalog Processors, TI. “By integrating all the major components of an AM335x-Processor-based-system into a single package, developers can quickly place a single SiP onto their boards and can still leverage all the software provided by TI to dramatically simplify their design.”

To help speed up development around the OSD3358, Octavo is also announcing the availability of the OSD3358 Development Platform from GHI Electronics featuring a capacitive touch screen and multiple industrial interfaces.

## SiP Metrics – Is there a Moore’s Law equivalent?

In the landmark paper of 1965, Gordon Moore[1] made an observation stating that with cost of manufacturing per device falling, it becomes economical to pack more and more devices in an IC chip. In his paper, Moore projected the number of devices in an IC chip would double every one to two years. This observation soon took the form of a proxy for future growth estimates in the semiconductor industry.

For decades, Moore’s law has been the benchmark for semiconductor technology development, eventually becoming a roadmap and a self-fulfilling prophecy for IC development.  Figure 1[2] shows the growth of the number of devices in a semiconductor chip over time and tracks well with Moore’s projection.

The popularity of Moore’s law was in its simplicity. The number of transistors is a meaningful and simple measure and generally tracks with system development. However, Moore’s law is not universally applicable to all microelectronic devices. One such device is a SiP.

SiPs are emerging as a distinct class of microelectronic products because of their unique ability to integrate silicon of different process technologies such as Digital, Analog, Power, and DRAM as well as include passives and other devices to build integrated solutions. It is therefore useful to study SiP development and see if there are logical Moore’s Law like trends that are evident. In the next section, we will discuss a possible trend for SiPs, the reduction of external connections, and make a proposal for a growth metric for SiP technologies.

The ultimate goal of SiPs is to enable a fully integrated stand-alone autonomous electronic system. Such a SiP would have its own power supply, microprocessor, input, output and passive devices and be capable of performing the required function entirely with no external wired connection. An ideal SiP would have no external pins (if it had its own power source) or only have 2 pins – for power and ground.  Since one of the purposes of a SiP is to reduce the number of wired connections we propose a figure of merit based on the reduction of these connections provided by using a SiP.

SiP “Figure of Merit” (FOM):  One can define a FOM based on the number of externally wired connections in a SiP. If a SiP reduces the number of connections of the chips on board (COB) by half, then FOM is 0.5.  If the SiP completely eliminates the need for external connections, therefore creating an autonomous system, then, in this ideal case, the FOM is 1. A system with no SiP means there was no reduction in interconnections to form a system. Such a system would have a FOM of 0.    Therefore, FOM can be defined by the formula,

$\text{Figure of Merit (FOM)} = \frac{\text{Number of Connections with COB}-\text{Number of Connections with SiP}}{\text{Number of Connections with COB}}$

In the chart (Figure 2) below there are a few examples FOM. A real-life test case system “A” is also included for reference. In system “A” by using SiP the total number of interconnects dropped from about 1200 to 700 pins which gives a FOM of 0.42.

As discussed in a previous post, one of the key areas holding back the development of SiPs is the lack of a metric to measure their effectiveness and development.  In this blog we have attempted to put forward a proposed metric tied to the reduction in number of external connections due to a SiP integration, which in turn correlates with the level of integration as a system. We will be using this metric to help demonstrate the value of our SiP devices.

We welcome your comments on this topic as we attempt to set a metric that can be used across the industry.

[1]  Cramming more components onto integrated circuits, Gordon Moore, Electronics, Volume 38, Number 8, April 19, 1965

[2] International Technology Roadmap for Semiconductors (ITRS) 2007

## System in Package: the Complement to Moore’s Law

Moore’s Law has served us well for over a half of a century.  It drove the semiconductor (SC) process technology roadmap.  It got us to think about putting more transistors on an integrated circuit to the point where it is no longer a nightmare to consider billions of transistors on one piece of silicon.  In fact, several years ago I began to use the phrase “transistors are becoming a buck a billion” to put a new perspective on the success of Moore’s Law.

But even with the great success the SC industry has had, we continue to find ourselves unable to accomplish the ultimate goal, a complete system on a chip.  Yes, we talk about System on Chip (SoC) technology as the solution (now what was the problem again?).  However, the advancements in IC technology have actually defeated the primary goal of SoC, the integration of a complete system on a single piece of silicon.  In the past I have actually suggested that it should be SSoC rather than SoC as all we have been able to do is a Sub-System on a Chip.

So why can’t we put a complete system on one device?  Why haven’t we, through all of the advances, been able to truly get the entire system on a single piece of silicon?  Let’s take a step back and look at the type of components that go into a system.  They include processors, memories, analog, power management, RF communications, sensors, energy scavengers, and many more. Each of which use a different SC process that has evolved in part by chasing Moore’s Law to optimize its peak performance.  We no longer have just one IC manufacturing process.  We have created processes to be optimized for specific needs.  There is a specific process for high performance microprocessors, another process for memories, another for high performance audio, another for power management, another for RF circuits . . . have you caught the drift?

You can argue that an optimal SC process should be able to include all of the different types of components.  However, the laws of physics as we know them today don’t allow this to happen.  We can mix different types of components onto a single process but significant compromises will have to be made.  The only way to achieve the optimal performance out of a system is to have each component use its own optimized process.  So you end up with a design where all of the digital circuits are integrated into a digital SoC , the analog circuits into an analog SoC, the power circuits into a power SoC, and so forth. (See figure to the right)

That leads me to a complementary capability introduced to the industry about a decade or so ago.  This new ability enabled different components from different SC processes to be integrated into a single package that can be used by system designers.  There are several ways to accomplish this and they have different names, such as Multi-Chip-Module (MCM), System on Module (SoM), or System in Package (SiP).  From our perspective, the concept of a System in Package (SiP) best describes the ultimate concept.  The reason for our use of SiP is simple:

• A System consists of many components including analog, digital, and power ICs, as well as other active circuits like transistors, diodes, MeMs and sensors. You also need to include passive devices like resistors, capacitors and inductors.
• In-Package means all of the components that make up the system are in a Single Package that looks like an IC.

So to the outside world a SiP looks like a complete electronic system in single package.

However, as a system designer, even with SiP technology bringing to together different SoC processes along with other electronic components a true complete System-In-Package is still hard to achieve.  I’ll give you a hint why I am saying this – the SiPs today still have pins on the package.  The ultimate electronic system should not need pins, right?  But I’ll save that discussion to a later post.  Let me get back to the topic.

What brought us to needing SiP technology can be best seen by going back to the origin of the integrated circuit and following its evolution.  But just as with the earlier “not needing pins” comment, we will discuss this evolution in more detail in a later blog.  For now I will simply say that as we optimized the manufacturing processes for the different kinds of circuits, the ability to put those different kinds of circuits onto the same SoC became difficult, if not impossible.  The only way to continue to integrate these different SoCs is through the use of a SiP.  The following figure attempts to describe that issue.

Now that we went through why SiPs are needed, if you want more information on how Octavo Systems is bringing this technology to the masses check out our series on SiP technology and the Challenges here.

Since the early 1960s, advances in semiconductor technology have been tracking Moore’s law. This “law”, based on a paper by Gordon Moore[i], states that the number of transistors per chip will double about every 18 months.  For decades Moore’s law has been the overarching benchmark for development in the Semiconductor industry, especially in regards to System-On-Chip (SoC) development.

Moore’s law, however, is not endlessly sustainable (for reasons we discuss in this post) and an alternative approach was needed. Since the 2000’s there has been a recognition that System-In-Package devices (SiPs) indeed have a distinct role in semiconductor technology development. The 2009 ITRS (International Technology Roadmap for Semiconductors) on SiPs (Figure to the Right) reflects this recognition and outlines the technologies that are uniquely enabled by SiP technology. It is now becoming evident that SoC progression and Moore’s law cannot solely define the semiconductor roadmap and SiPs play a major and complementary role.

Will SiPs emulate the rapid advancements seen in SoCs? At Octavo we believe the answer is YES. We believe there are key areas for innovation to spur the wider and faster adoption of SiPs.  Outlined below are a few of the challenges that we are working to address.

First, a meaningful metric for SiP progression similar to Moore’s law is required.  A standardized metric will allow comparison and evaluation of SiP technologies to one another and compare solutions. Moore’s law simply uses the number of transistor in a chip as the metric.  For System-in-Package the metric will have to be different and likely more complex. While it may include the number of transistors as with SoCs, extent of heterogeneous functional integration and the hierarchy of system integration achieved by SiP are some of the few factors that could be taken into consideration to define a meaningful metric. (We propose our metric in this post)

Secondly, SiP development will require development of supporting manufacturing infrastructure. SiPs by necessity will use most of the existing SoC manufacturing base which is not yet optimized for SiPs. This will bring many challenges[ii] to SiP development.

Here are a few of these challenges

1. Supply chain management for constituent SoCs
2. A uniform definition of known-good-die (KGD) between supplier and user
3. Complexity of system design which includes passives, MEMs, and other non-traditional circuit elements
4. Packaging and thermal management
5. Functional testing
6. Rapid prototyping and validation
7. High volume manufacturing
8. Reliability in unusual or harsh environments

[i]  Cramming more components onto integrated circuits, Gordon Moore, Electronics, Volume 38, Number 8, April 19, 1965

[ii] The road ahead for SiPs, Darvin Edwards & Masood Murtuza, Solid State Technology, Feb. 2011.